Crosstalk in Modern On-Chip Interconnects (eBook)

Brajesh Kumar Kaushik received the B.E. degree in Electronics and Communication Engineering from the D.C.R. University of Science and Technology (formerly C. R. State College of Engineering), Murthal, Haryana, in 1994, the M.Tech degree in Engineering Systems from Dayalbagh Educational Institute, Agra, India, in 1997, and the PhD degree under AICTE-QIP scheme from the Indian Institute of Technology Roorkee, Roorkee, India, in 2007. He served at Vinytics Peripherals Pvt. Ltd., Delhi from 1997 to 1998 as the Research and Development Engineer for microprocessor-, microcontroller-, and DSP processor-based systems.He joined the department of Electronics and Communication Engineering, G.B. Pant Engineering College, Pauri Garhwal, Uttarakhand, India as a Lecturer in July, 1998, where later he served as an Assistant Professor from May 2005 to May 2006 and an Associate Professor from May 2006 to December 2009. He is currently serving as Associate Professor in the department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee. His research interests include high-speed interconnects, low-power VLSI design, carbon nanotube-based designs, organic thin-film transistor design and modeling, and spintronics-based devices and circuits. He has published extensively in several national and international journals and conferences of repute. Dr. Kaushik is a reviewer of many international journals belonging to various publication houses such as IEEE, IET, Elsevier, Springer, Emerald, Taylor and Francis, etc. He has also delivered many keynote addresses in reputed international and national conferences. He holds the position of Editor and Editor-in-Chief of various journals in the field of VLSI and Microelectronics. Dr. Kaushik is Editor-in-Chief of International Journal of VLSI Design and Communication System (VLSICS), AIRCC Publishing Corporation. He also holds the position of Editor of Microelectronics Journal (MEJ), Elsevier Inc.; Journal of Engineering, Design and Technology (JEDT), Emerald Group Publishing Limited; and Journal of Electrical and Electronics Engineering Research (JEEER), Academic Journals. He is a Senior Member of IEEE and has received many awards and recognitions from the International Biographical Center, Cambridge, U.K. His name has been listed in Marquis Who’s Who in Science and Engineering and Marquis Who’s Who in the World. Vobulapuram Ramesh Kumar received the B.Tech degree in Electronics and Communication Engineering from Bapatla Engineering College, Andhra Pradesh, in 2007, and the M.Tech degree from National Institute of Technology Hamirpur, in 2010. He is currently working towards the PhD degree from Indian Institute of Technology Roorkee, India. His current research interests include time domain numerical methods to approach fast transients characterization techniques, modeling of VLSI on-chip interconnects, carbon based nano interconnects and through silicon vias.  Amalendu Patnaik received his PhD in Electronics from Berhampur University in 2003. He is currently serving as Associate Professor in the department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee. He served as a Lecturer in National Institute of Science and Technology, Berhampur, India. During 2004-05, he has been to University of New Mexico, Albuquerque, USA as a Visiting Scientist. He has published more than 50 papers in journal and conferences, co-authored one book on Engineering Electromagnetics, and one book chapter on Neural Network for Antennas in Modern Antenna Handbook from Wiley. Besides this, he has presented his research work as short courses/tutorials in many national and international conferences. His current research interests include array signal processing, application of soft-computing techniques in Electromagnetics, CAD for patch antennas, EMI and EMC. He was awarded the IETE Sir J. C. Bose Award in 1998 and BOYSCAST Fellowship in 2004-05 from Department of Science and Technology, Government of India. Dr. Patnaik is a life member of Indian Society for Technical Education (ISTE), Senior Member of IEEE and IEEE AP-S Region 10 Distinguished Speaker.

Preface 6
Contents 9
About the Authors 12
About the Book 14
1 Introduction to On-Chip Interconnects and Modeling 15
Abstract 15
1.1 Introduction 15
1.2 Evolution of Interconnect Materials 16
1.2.1 Carbon Nanotubes (CNTs) 17
1.2.2 Graphene Nanoribbons (GNRs) 18
1.3 Modeling of On-Chip Interconnects 18
1.4 Introduction to FDTD Method 20
1.4.1 Central Difference Approximation 21
References 22
2 Interconnect Modeling, CNT and GNR Structures, Properties, and Characteristics 24
Abstract 24
2.1 Interconnect Modeling Approaches 24
2.1.1 Lumped Model with CMOS Driver 24
2.1.2 Distributed Model with Resistive Driver 25
2.1.3 Distributed Model with CMOS Driver 26
2.2 Carbon Nanotubes 27
2.2.1 Basic Structure of CNTs 27
2.2.2 Semiconducting and Metallic CNTs 31
2.2.3 Properties and Characteristics of CNTs 33
2.2.3.1 Strength and Elasticity 33
2.2.3.2 Thermal Conductivity and Expansion 34
2.2.3.3 Field Emission 34
2.2.3.4 Aspect Ratio 34
2.2.3.5 Absorbent 35
2.2.3.6 Conductivity 35
2.2.4 Conductivity Comparison 35
2.2.4.1 SWCNT Conductivity 36
2.2.4.2 MWCNT Conductivity 36
2.2.5 MWCNT Interconnect Modeling 37
2.2.5.1 MTL and ESC Models of MWCNT Interconnect 38
2.2.6 MWCNT Performance Analysis 41
2.3 Graphene Nanoribbons 42
2.3.1 Basic Structure of GNRs 42
2.3.2 Semiconducting and Metallic GNRs 44
2.3.3 Properties and Characteristics of GNRs 44
2.3.3.1 Mean Free Path of GNR 45
2.3.4 Conductivity Comparison 46
2.3.5 MLGNR Interconnect Modeling 47
2.3.6 MLGNR Performance Analysis 49
References 51
3 FDTD Model for Crosstalk Analysis of CMOS Gate-Driven Coupled Copper Interconnects 55
Abstract 55
3.1 Introduction 55
3.2 Motivation 56
3.3 FDTD Model of CMOS Gate-Driven Cu Interconnects 59
3.3.1 FDTD Model of Coupled Interconnects 60
3.3.2 Incorporation of Boundary Constraints 62
3.4 Validation of the Model 65
3.5 Extended Three Coupled Interconnect Lines 68
3.6 Summary 70
References 71
4 FDTD Model for Crosstalk Analysis of Multiwall Carbon Nanotube (MWCNT) Interconnects 72
Abstract 72
4.1 Introduction 72
4.2 Equivalent Single Conductor Model of the MWCNT Interconnect 74
4.2.1 Resistance 76
4.2.2 Inductance 76
4.2.3 Capacitance 78
4.3 FDTD Model of MWCNT Interconnect 79
4.3.1 The MWCNT Interconnect Line 79
4.3.2 Boundary Condition at Near-End Terminal 81
4.3.3 Boundary Condition at Far-End Terminal 82
4.4 Validation of the Model 83
4.5 Sensitivity Analysis 86
4.5.1 Sensitivity Analysis for Number of Conducting Channels 86
4.5.2 Sensitivity Analysis for Contact Resistance 87
4.6 Summary 88
References 88
5 Crosstalk Modeling with Width Dependent MFP in MLGNR Interconnects Using FDTD Technique 91
Abstract 91
5.1 Introduction 91
5.2 Equivalent Single Conductor Model of the MLGNR Interconnect 92
5.2.1 Transient Analysis of MTL and ESC Models 95
5.3 FDTD Model of the MLGNR Interconnect 96
5.4 Results and Discussion 99
5.4.1 Analysis of Mean Free Path, Resistance, and Propagation Delay with Rough Edges 100
5.4.2 Crosstalk-Induced Delay 101
5.4.3 Performance Comparison Between Cu and MLGNR Interconnects 103
5.5 Summary 105
References 105
6 An Efficient US-FDTD Model for Crosstalk Analysis of On-Chip Interconnects 107
Abstract 107
6.1 Introduction 107
6.2 Development of Proposed US-FDTD Model 108
6.2.1 Modeling of Coupled On-Chip Interconnects 109
6.2.2 Modeling of CMOS Driver 111
6.2.3 Modeling of Driver-Interconnect-Load 112
6.2.4 Stability Analysis 116
6.3 Simulation Setup and Results 117
6.3.1 Transient Analysis 118
6.3.2 Crosstalk Induced Noise Peak, Width and Delay Analysis 119
6.3.3 Unconditional Stability of the Proposed Model 120
6.3.4 Efficiency of the Proposed Model 121
6.3.5 Comparison with 3D Simulations 122
6.4 Performance Comparison of Cu, MWCNT and MLGNR Interconnects 123
6.5 Summary 125
References 125