VLSI Architectures for Modern Error-Correcting Codes
Crc Press Inc (Verlag)
978-1-4822-2964-6 (ISBN)
VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation.
The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included.
More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.
Xinmiao Zhang received her Ph.D in electrical engineering from the University of Minnesota, Twin Cities, USA. She is currently an Associate Professor in the Department of Electrical and Computer Engineering at The Ohio State University. Previously, she was a Timothy E. and Allison L. Schroeder Associate Professor at Case Western Reserve University, Cleveland, Ohio. Between her academic positions, she continued her research on error-correcting codes at SanDisk/Western Digital Corporation. She has also been a visiting professor at Qualcomm and spent her sabbatical leave at the University of Washington, Seattle, USA. Her research focuses on VLSI architecture design for communications, digital signal processing, and cryptography. She is a recipient of the National Science Foundation Faculty Early Career Development (CAREER) Award.
Finite Field Arithmetic. VLSI Architecture Design Fundamentals. Root Computations for Polynomials Over Finite Fields. Reed-Solomon Encoder and Hard-Decision Decoder Architectures. Algebraic Soft-Decision Reed-Solomon Decoder Architectures. Interpolation-Based Chase and Generalized Minimum Distance Decoders. BCH Encoder and Decoder Architectures. Binary LDPC Codes and Decoder Architectures. Non-Binary LDPC Decoder Architectures.
| Zusatzinfo | 37 Tables, black and white; 124 Illustrations, black and white |
|---|---|
| Verlagsort | Bosa Roca |
| Sprache | englisch |
| Maße | 156 x 234 mm |
| Gewicht | 725 g |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 1-4822-2964-1 / 1482229641 |
| ISBN-13 | 978-1-4822-2964-6 / 9781482229646 |
| Zustand | Neuware |
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