Introduction

Nicolas Posseme; Maxime Darnon

In 1947, the bipolar transistor was invented by Bardeen, Brattain and Shockley. Following this invention, in 1957, Kilby created five transistors simultaneously, forming the first integrated circuit (IC). In 1960, the first metal oxide semiconductor field effect transistor (MOSFET) on a silicon substrate with SiO2 gate insulator was fabricated. The MOSFETs are slow compared to bipolar devices but are easier to fabricate and have a higher layout density. But both devices (bipolar and MOSFET) suffer from high power dissipation and have a restricted use in large integrated chip.

In 1963, the invention of the complementary metal oxide semiconductor (CMOS) marked a new milestone in the area of semiconductors. Indeed, the CMOS transistor has lower power dissipation and the possibility to integrate millions of CMOS transistors onto a chip. Since then, ICs have evolved from a 100-transistors chip in 1966 to multibillion transistors circuits in 2010, with the smallest device of less than 20 nm.

Semiconductor fabrication is composed of three major parts, front-end-of-line (FEOL), middle-end-of-line (MEOL) and back-end-of-line (BEOL), including different main steps such as deposition, lithography, etching and cleaning. The whole process flow represents several hundreds of steps for the manufacturing of chips.

The FEOL processes correspond to isolation, gate patterning, spacer, extension and source/drain implantation, silicide formation and dual stress liner formation.

The MEOL is mainly gate contact formation, which becomes more and more challenging as device dimensions are reduced [MEB 14].

The BEOL allows transistor functionality by electrically interconnecting transistors. Interconnects are composed of insulating layers (dielectric) and metal levels. Interconnects (see Figure 1.1) are composed of several metal levels. Each metal level is composed of horizontal metallic lines connected to the lower and upper metal levels through short vertical lines called vias.

The combination of aluminum (Al) metal lines and silicon dioxide (SiO2) as dielectric material has been used so far for interconnects in ICs. The problem lies with the constant downscaling in device dimensions resistive–capacitive (RC) delay (product of the resistance of the metal lines and their intercapacitance), dynamic power consumption (~α C.V2f for a wire, where f is the frequency of digital signal, α is the wire activity factor, V corresponds to the voltage between the two digital levels and C is the total interconnect capacitance of a wire length) and cross-talk noise. These are becoming the main issues for devices with high performances [YAM 00, DEL 99].

Indeed, as shown in Figure 1.2, the reduction of device dimensions leads to an improvement of the device performances characterized by a decrease in the gate delay as a function of the generation. But from the 0.25 μm technology nodes, interconnects (SiO2 + Al) become the limiting factor for high-performance devices leading to an increase in the total delay (see Figure 1.2).

Therefore, it is mandatory for BEOL interconnect wiring to be smaller, but also to cater for an increase in device density inducing important delay increases. Smaller dimensions require the introduction of new materials and new integration schemes.

A model at the first order can be used to estimate interconnect RC delay as shown in Figure 1.3.

The resistance of one interconnect line is given by:

=ρ.LW.H

where ρ is the metal resistivity, and L, W and H are the metal line length, width and height, respectively.

The level-to-level capacitance is defined by:

V=ε0.k.L.WE

where E and k are the dielectric film thickness between two levels and dielectric constant, respectively, and ε0 is the permittivity of free space.

While the capacitance between the two interconnect lines is:

L=ε0.k.L.He

where e is the space between two lines.

For this simple structure, the total line capacitance can be approximated by combining [1.2] and [1.3] as follows:

=CV+CL=ε0.k.(L.WE+L.He)

Related to [1.1] and [1.4], the RC delay defined as the product of the resistance of the metal lines and their intercapacitance is:

=ε0.k.ρL2(1HE+1we)

Therefore, related to [1.5] with the constant scaling down in dimension, the RC delay increases (see Figure 1.2). In addition, the dynamic power consumption for a wire and the cross-talk noise change with the capacitance and thus become larger when the dimensions shrink. As a result, interconnects are becoming the major limiter to device performance when dimensions are reduced.

To overcome this limitation, it was proposed to:

– replace the aluminum wiring with a metal presenting lower resistivity (ρ) [KEI 03];

– switch from conventional SiO2 (k ≈ 4.2) to an insulator with lower dielectric constant (low-k) [ROU 05, HOO 05, JOU 07a].

These changes marked a new milestone in the history of interconnects with the introduction of new integration processes and new materials.

1.1 Integration processes related to copper introduction

With a lower resistivity of about 30% compared to aluminum, copper was chosen as a new metal for interconnects [KEI 03].

Copper was introduced by IBM for the first time in a product in 1997 and since then, has widely been adopted by the semiconductor industry [VOL 10]. But switching from aluminum to copper implied to revisit the integration scheme in the BEOL. Indeed, copper is very difficult to etch using conventional plasma etching temperatures (40–60°C) due to the formation of non-volatile compounds [LEE 97, HOW 91, OHN 98]. This difficulty implied the modification of patterning and integration processes switching from metal patterning followed by dielectric filling to dielectric patterning followed by copper filling, as shown in Figure 1.4. This last approach is called damascene, referring to a method that begins by dielectric layer deposition, followed by etching structures (trenches or holes) into the dielectric.

To minimize the risk of metallic contamination by copper, a metallic barrier, usually made up of tantalum/tantalum nitride (Ta/TaN), is deposited before the copper. This step is then followed by the filling of structures with copper. A chemical–mechanical planarization (CMP) is finally used to remove the excess metal.

If only trenches or holes are fabricated, the method is called single damascene. In the dual damascene approach, both holes and trenches are etched into a dielectric followed by a metal fill and CMP. Since dual damascene forms at trenches and holes with one metal deposition and one CMP step, it is the favored approach. Dual damascene methods reduce the number of process steps, thus reducing fabrication costs.

1.2 Dielectric material with low-k value (<4)

The dielectric constant of materials is given by the Clausius–Mossotti equation as follows:

−1k+2=43πNα

where k is the dielectric constant of the material, N is the number of molecules per volume unit (density) in the material and α is its total...