Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

Part I: Introduction and Prior Art.- Timing Closure for Multi-Million-Gate Integrated Circuits.- State of the Art in Physical Synthesis.- Part II: Local Physical Synthesis and Necessary Analysis Techniques.- Buffer Insertion during Timing-Driven Placement.- Bounded Transactional Timing Analysis.- Gate Sizing During Timing-Driven Placement.- Part III: Broadening the Scope of Circuit Transformations.- Physically-Driven Logic Restructuring.- Logic Restructuring as an Aid to Physical Retiming.- Broadening the Scope of Optimization using Partitioning.- Co-Optimization of Latches and Clock Networks.- Conclusions and Future Work.