Wireless Receiver Architectures and Design - Tony J. Rouphael

Wireless Receiver Architectures and Design (eBook)

Antennas, RF, Synthesizers, Mixed Signal, and Digital Signal Processing

Tony J. Rouphael (Autor)

eBook Download: PDF | EPUB

2014 | 1. Auflage
502 Seiten
Elsevier Science (Verlag)
978-0-12-378641-8 (ISBN)

Wireless Receiver Architectures and Design presents the various designs and architectures of wireless receivers in the context of modern multi-mode and multi-standard devices. This one-stop reference and guide to designing low-cost low-power multi-mode, multi-standard receivers treats analog and digital signal processing simultaneously, with equal detail given to the chosen architecture and modulating waveform. It provides a complete understanding of the receiver's analog front end and the digital backend, and how each affects the other. The book explains the design process in great detail, starting from an analysis of requirements to the choice of architecture and finally to the design and algorithm development. The advantages and disadvantages of each wireless architecture and the suitability to a standard are given, enabling a better choice of design methodology, receiver lineup, analog block, and digital algorithm for a particular architecture.

Whether you are a communications engineer working in system architecture and waveform design, an RF engineer working on noise and linearity budget and line-up analysis, a DSP engineer working on algorithm development, or an analog or digital design engineer designing circuits for wireless transceivers, this book is your one-stop reference and guide to designing low-cost low-power multi-mode multi-standard receivers. The material in this book is organized and presented to lead you from applied theory to practical design with plenty of examples and case studies drawn from modern wireless standards.

Provides a complete description of receiver architectures together with their pros and cons, enabling a better choice of design methodology
Covers the design trade-offs and algorithms between the analog front end and the digital modem - enabling an end-to-end design approach
Addresses multi-mode multi-standard low-cost, low-power radio design - critical for producing the applications for Smart phones and portable internet devices

Wireless Receiver Architectures and Design presents the various designs and architectures of wireless receivers in the context of modern multi-mode and multi-standard devices. This one-stop reference and guide to designing low-cost low-power multi-mode, multi-standard receivers treats analog and digital signal processing simultaneously, with equal detail given to the chosen architecture and modulating waveform. It provides a complete understanding of the receiver's analog front end and the digital backend, and how each affects the other. The book explains the design process in great detail, starting from an analysis of requirements to the choice of architecture and finally to the design and algorithm development. The advantages and disadvantages of each wireless architecture and the suitability to a standard are given, enabling a better choice of design methodology, receiver lineup, analog block, and digital algorithm for a particular architecture. Whether you are a communications engineer working in system architecture and waveform design, an RF engineer working on noise and linearity budget and line-up analysis, a DSP engineer working on algorithm development, or an analog or digital design engineer designing circuits for wireless transceivers, this book is your one-stop reference and guide to designing low-cost low-power multi-mode multi-standard receivers. The material in this book is organized and presented to lead you from applied theory to practical design with plenty of examples and case studies drawn from modern wireless standards. Provides a complete description of receiver architectures together with their pros and cons, enabling a better choice of design methodology Covers the design trade-offs and algorithms between the analog front end and the digital modem - enabling an end-to-end design approach Addresses multi-mode multi-standard low-cost, low-power radio design - critical for producing the applications for Smart phones and portable internet devices

Preface

Background

The advent of modern wireless devices, such as smart phones and MID1 terminals, has revolutionized the way people think of personal connectivity. Such devices encompass multiple applications ranging from voice and video to high-speed data transfer via wireless networks. The voracious appetite of twenty-first century users for supporting more wireless applications on a single device is ever increasing. These devices employ multiple radios and modems that cover multiple frequency bands and multiple standards with a manifold of wireless applications often running simultaneously. This insatiable requirement for multistandard multimode devices has ushered in new innovations in wireless transceiver designs and technologies that led and will continue to lead the way to highly integrated radio solutions in the form of SoCs.2 These solutions include several radios and digital modems all designed on a single chip.

The design of such futuristic wireless radios and modems, capable of supporting multiple standards and modes, is drastically different from traditional designs supporting a single standard. The complications stem due to the high level of integration, low power, and low cost requirements imposed on the chip manufacturers. Until recently, most designers and architects designed for one particular application or another, which in turn meant familiarity with certain modem or radio architecture targeted for a certain wireless standard. However, designing future wireless devices, which entail designing for multimode and multistandard wireless applications, will require the radio engineer to be familiar with all facets and nuances of various transceiver architectures. This in essence will help maximize the efficiency of the design, lower the overall cost of the device, and allow for coexistence and simultaneous operations of various radios.

The intent of this book is to address the various designs and architectures of wireless receivers in the context of modern multimode and multistandard devices. The aim is to present a unique coherent and comprehensive treatment of wireless receivers from analog front ends to mixed signal design and frequency synthesis with equal emphasis on theory and practical design. Throughout the text, the design process is characterized by a close interaction between architecture on the one hand and algorithm design on the other with particular attention paid to the whole design process. This is in contrast to most other wireless design books that focus either on the theory or implementation. The focus will be on architecture and partitioning between mixed signal, digital and analog signal processing, analysis and design trade-offs, block level requirement, and algorithms. The reader will learn how certain design trade-offs in the analog back end, for example, can positively or negatively impact the design in the analog front end and vice versa. Furthermore, the reader will learn how the choice of certain algorithms for a given architecture can reduce the cost and design cycle. Conversely, how the choice of certain parameters or blocks in the lineup, such as filters, mixers, and amplifiers can significantly ameliorate the performance of the wireless receiver.

Scope

The intended audience of this book is engineers, researchers, and academics working in the area of wireless communication receivers. More precisely, the book is targeted toward engineers and researchers focused on designing low-power low-cost multimode multistandard receivers of the twenty-first century. It targets professionals who seek a comprehensive treatment and deep practical and theoretical understanding of wireless receiver design.

The book is divided into eight chapters:

• Chapter 1 focuses on antenna theory, transmission lines, and matching networks. The chapter provides an overview of antenna design and analysis. Topics such as radiation fields, gain, directivity and efficiency, matching circuits and networks, and transformers are addressed. The chapter concludes with a discussion on the most common types of antennas notably the monopole, the dipole, the patch, and the helical antennas.

• Chapter 2 addresses microwave network design and analysis. The chapter is divided into three major sections. In Section 2.1, we address the various circuit network models and their advantages and disadvantage particularly the impedance and admittance multiport network model, the hybrid network model, and the scattering parameters network model. Section 2.2 presents the topics of signal flow graphs, power gain equations and analysis, and stability theory. In Section 2.3, we discuss the most common types of two-port and three-port devices found in low-power wireless receivers.

• Chapter 3 is focused on noise in wireless receivers and how it manifests itself in circuits and components. The first section discusses thermal noise and how it appears in electronic components. Topics such as noise figure at the component and system level and how it impacts the performance of the receiver are discussed in some detail. Next, we introduce the concept of phase noise and present both Leeson's model and the Lee-Hajimiri model. The impact of phase noise on performance is also addressed. Finally, external noise sources due to interferers and blockers are discussed. The impact of coexistence of multiple radios on a single chip and its impact on the desired received signal is also discussed.

• Chapter 4 is concerned with system nonlinearity and its impact on receiver performance and design. The chapter focuses mainly on weakly nonlinear systems with a brief mention strongly nonlinear systems. The various nonlinear phenomena are first classified. The chapter then delves into a discussion on memoryless nonlinearities using power series methods. The chapter concludes with a discussion on nonlinear systems with memory and the Volterra series techniques used to model them. The chapter contains several appendices.

• Chapter 5 is concerned with signal sampling and distortion. It starts with describing the sampling and reconstruction processes of baseband and bandpass signals and then examines the various degradations caused by the signal conversion and sampling imperfections. Topics such as quantization noise, sampling clock jitter, impact of phase noise on the sampling clock, signal overloading and clipping are discussed. The anti-aliasing filtering requirements and their impact on signal quality are also examined. An exact formulation of the quantization noise and a re-derivation of signal-to-quantization-noise ratio that takes into account the statistics of the input signal are also presented.

• Chapter 6 is concerned with analog to digital conversion and the architecture of the various data converters. The various building blocks of the ADC such as track and hold amplifiers and comparators are studied. The impact of aperture time accuracy clock feedthrough, and charge injection and their impact on signal SNR (signal to noise ratio) are also discussed. Next the Nyquist converter as a class of data converters is discussed. We delve into the architectural details of the FLASH, pipelined, and folding ADC architectures. Key performance parameters such as dynamic range, SNR, and harmonic distortion among others are also discussed. Next, we discuss oversampled converters and contrast it with Nyquist converters. The basic loop dynamics are derived. The architectures of continuous-time and discrete-time ?? modulators are presented and their advantages and disadvantages are also contrasted. The MASH converter architecture is then presented and its pros and cons versus a single loop converter are also discussed.

• Chapter 7 presents two topics that deal with loops: the automatic gain control (AGC) loop algorithm and frequency synthesis phase-locked loop (PLL) design. While discussing the AGC loop, we discuss topics such as receiver lineup and gain, noise and noise figure, linear optimization, and dynamic range. We also discuss the digital signal processing implementation of the AGC loop. Closed loop dynamics are also presented in some detail. In the second portion of the chapter we discuss frequency synthesis. The Linear PLL model is discussed and performance parameters pertaining to error convergence, order and type, stability, and operating range are presented. The various blocks that constitute the PLL such as the frequency and phase detector, loop filter, and VCO are discussed. Finally, we focus on synthesizer architectures relevant to integer-N and fractional-N PLLs where we discuss various programmable digital counters such as the dual modulus prescalar and counters based on ? ? modulators. The performance of both architectures is evaluated especially with respect to spurs, loop bandwidth, and resolution.

• Chapter 8 is focused on receiver architecture. In particular, we study the direct conversion architecture, the superheterodyne architecture, and the low-IF architecture. We present the nuances and pros and cons of each of the architectures and discuss the various performance parameters. Two appendices concerning DC offset compensation and IQ imbalance compensation are also provided.

Tony J.RouphaelSan Diego, California

October 2013

1 MID stands for Mobile Internet Device

2 SoC stands for system on...

Erscheint lt. Verlag	26.6.2014
Sprache	englisch
Themenwelt	Technik ► Elektrotechnik / Energietechnik
Themenwelt	Technik ► Nachrichtentechnik
ISBN-10	0-12-378641-X / 012378641X
ISBN-13	978-0-12-378641-8 / 9780123786418

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