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Behavioral Synthesis

Digital System Design Using the Synopsys Behavioral Compiler

(Autor)

Buch | Softcover
256 Seiten
1996
Prentice Hall (Verlag)
978-0-13-569252-3 (ISBN)
88,65 inkl. MwSt
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Working engineers, managers and students of electronic design.

The newest tool for high level digital system design is behavioral synthesis, an evolutionary step up from logic synthesis. This is the first book on that tool.
56925-1 Behavioral synthesis is now a reality. After nearly twenty years of academic and industrial research and development, designers are reaping the rewards of this technology, which brings increased productivity, improved design quality, and faster time to market. This book gives a designer's-eye view of this exciting new EDA technology. The first six chapters provide a detailed description of what goes on under the hood of an industrial-strength behavioral synthesis product, the Synopsys Behavioral Compiler, with copious notes and tips on how to use this knowledge to get the most out of this powerful new tool. * Introduction to the behavioral design flow * Behavioral synthesis representations and processes * Writing HDL descriptions for behavioral synthesis * Managing I/O timing * Behavioral Compiler commands and options * Interpreting error messages The next five chapters provide detailed case studies, representing a variety of design problems: * IIR and FIR filters * Video compression and translation from C to HDLs * Data encryption * Packet routing The examples are given in both VHDL and Verilog.
Machine-readable versions, along with complete synthesis reports, are provided on the accompanying diskette (requires Syopsys Behavioral Compiler to synthesize).

 1. Introduction.


Design Flow. Simulation and Verification. RTL and Behavioral Design. Behavioral Compiler Design Flow.



 2. Behavioral Compiler.


Inputs. Behavioral Compilation: Internals.



 3. HDL Descriptions.


The Design. Behavioral Processes. Clock and Reset. I/O Operations. Flow of Control. Memory Inference. synthetic Components. Preserved Functions. Pipelined Components. Random Logic.



 4. I/O Modes.


Cycle-Fixed Mode. Superstate-Fixed Mode. Free-Floating Mode. Control Unit Registers.



 5. Explicit Directives and Constraints.


Labeling. Scheduling Constraints. Options. Test Benches; Simulation.



 6. Reports.


Timing Report. Reservation Tables. State Machine Reports. Error Messages.



 7. FIR Filter.


Initial Design. Synthesis. Simulation. Decreasing Cost.



 8. IIR Filter: Handshaking I/O Protocal.


Initial Design. Simulation. Synthesis. Speeding Up the Clock.



 9. The Inverse Discrete Cosine Transform: C to HDL.


Initial C Code. Translation into HDL. Simulation.



10. The Data Encryption Standard: Random Logic.


General Description. HDL Description. Synthesis. Use of Design Ware.



11. Packet Router.


A. Construction Design Ware.



B. Sythesizable Subsets.

Erscheint lt. Verlag 1.7.1996
Verlagsort Upper Saddle River
Sprache englisch
Gewicht 734 g
Themenwelt Mathematik / Informatik Informatik Theorie / Studium
Informatik Weitere Themen CAD-Programme
Technik Elektrotechnik / Energietechnik
ISBN-10 0-13-569252-0 / 0135692520
ISBN-13 978-0-13-569252-3 / 9780135692523
Zustand Neuware
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