CMOS and Beyond

Tsu-Jae King Liu is the Conexant Systems Distinguished Professor, Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. A co-inventor of the FinFET, she has been awarded the IEEE Kiyo Tomiyasu Award (2010), the Electrochemical Society Thomas D. Calinan Award (2011), and the Intel Outstanding Researcher Award (2012). She is a Fellow of the IEEE. Kelin Kuhn is an Intel Fellow and Director of Advanced Device Technology in the Technology and Manufacturing Group at Intel Corporation. She is responsible for research on new device architectures and has been awarded two Intel Achievement Awards, one for high-k metal-gate (2006) and one for Trigate (2008), as well as the IEEE Paul Rappaport Award (2013). She is a Fellow of the IEEE.

1. Energy-efficiency limits of digital circuits based on CMOS transistors Elad Alon; 2. Beyond transistor scaling: alternative device structures for the terascale regime Zachery A. Jacobson and Kelin J. Kuhn; 3. Benchmarking alternative device structures for the terascale regime Zachery A. Jacobson and Kelin J. Kuhn; 4. Extending CMOS with negative capacitance Asif Islam Khan and Sayeef Salahuddin; 5. Designing a low voltage, high current tunneling transistor Sapan Agarwal and Eli Yablonovitch; 6. Tunnel transistors Alan Seabaugh, Zhengping Jiang and Gerhard Klimeck; 7. Graphene and 2D crystal tunnel transistors Qin Zhang, Pei Zhao, Nan Ma, Grace (Huili) Xing and Debdeep Jena; 8. Bilayer pseudospin field effect transistor Sanjay Bannerjee, Frank Register and Dharmendar Reddy; 9. Computation and learning with metal-insulator transitions and emergent phases in correlated oxides You Zhou, Sieu D. Ha and Shriram Ramanathan; 10. The piezo-electronic transistor Paul M. Solomon, Bruce G. Elmegreen, Matt Copel, Marcelo A. Kuroda, Susan Trolier-McKinstry, Glenn J. Martyna and Dennis M. Newns; 11. Mechanical switches Tsu-Jae King Liu and Rhesa Nathanael; 12. Nanomagnetic logic: from magnetic ordering to magnetic computing György Csaba, Gary H. Bernstein, Alexei Orlov, Michael T. Niemier, X. Sharon Hu and Wolfgang Porod; 13. Spin torque majority gate logic Dmitri E. Nikonov and George I. Bourianoff; 14. Spin wave phase logic Alexander Khitun; 15. Interconnect considerations Ahmet Ceyhan, Shaloo Rakheja and Azad Naeemi.