VLSI Design for Manufacturing: Yield Enhancement
Springer-Verlag New York Inc.
978-1-4612-8816-9 (ISBN)
1. Yield Estimation and Prediction.- 1.1. Introduction.- 1.2. The VLSI Fabrication Process.- 1.3. Disturbances in the IC Manufacturing Process.- 1.4. Measures of Process Efficiency.- 1.5. Discussion.- 1.6. Overview of the Sequel.- 2. Parametric Yield Maximization.- 2.1. Introduction.- 2.2. Design Centering and Worst Case Design with Arbitrary Statistical Distributions.- 2.3. Example of Worst Case Design.- 2.4. A Dimension Reduction Procedure.- 2.5. Fabrication Based Statistical Design of Monolithic IC’s.- 3. Statistical Process Simulation.- 3.1. Introduction.- 3.2. Statistical Process Simulation.- 3.3. Tuning of Process Simulator with PROMETHEUS.- 3.4. The Process Engineer’s Workbench.- 4. Statistical Analysis.- 4.1. Statistical Timing Simulation.- 4.2. An Improved Worst-Case Analysis Procedure.- 4.3. Optimal Device and Cell Design Using FABRICS.- 5. Functional Yield.- 5.1. Introduction.- 5.2. Basic Characteristics of Spot Defects.- 5.3. Yield Modeling Using Virtual Layout.- 5.4. Monte Carlo Approach to Functional Yield Prediction.- 5.5. Yield Computations for VLSI Cell.- 6. Computer-Aided Manufacturing.- 6.1. Motivation.- 6.2. Overview of the CMU-CAM System.- 6.3. Statistical Process Control: The Unified Framework.- 6.4. CMU-CAM Software System.- 6.5. Computational Examples.- 6.6. Conclusions.- References.
Reihe/Serie | The Springer International Series in Engineering and Computer Science ; 86 |
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Zusatzinfo | XII, 292 p. |
Verlagsort | New York, NY |
Sprache | englisch |
Maße | 155 x 235 mm |
Themenwelt | Technik ► Elektrotechnik / Energietechnik |
ISBN-10 | 1-4612-8816-9 / 1461288169 |
ISBN-13 | 978-1-4612-8816-9 / 9781461288169 |
Zustand | Neuware |
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