High-Performance D/A-Converters (eBook)

Martin Clara received the M.Sc. degree in electrical engineering from Vienna University of Technology, Austria, in 1996 and the Ph.D. degree in electronics from Graz University of Technology, Austria, in 2009.In 1997 he joined Siemens Microelectronics’ Design Center in Villach, Austria, as an Analog Design Engineer, mainly working on BiCMOS and CMOS linear circuits.From 2000 to 2009 he was with Infineon Technologies’ Design Center in Villach,Austria, where he designed data converters, linear circuits and RF building blocks in deep-submicron and nanometer CMOS technologies.Since 2009 he is senior engineer for analog/mixed-signal and RF-design at LANTIQ’s design center, based in Villach, Austria.His main interests include the implementation of low-voltage and high dynamic range analog front-ends in advanced CMOS technologies, the concept and design of highperformance data converters, as well as RF-CMOS design.

Application to Digital Transceivers 4
Preface 6
Contents 10
Acronyms and Abbreviations 14
List of Symbols 16
Chapter 1 Introduction 24
1.1 Integrated D/A-Converters 24
1.2 DACs for Highly Integrated Transceivers 30
1.3 The Ideal D/A-Converter 34
1.3.1 The Non Return-to-Zero DAC 35
1.3.2 The Return-to-Zero DAC 37
1.4 The Current-Steering DAC 39
1.4.1 General Description 39
1.4.2 Single-Polarity and Dual-Polarity Current Cells 41
1.4.3 Passive and Active Output Stage 41
1.5 Array Coding 43
1.5.1 Unary Array 43
1.5.2 Binary Array 44
1.5.3 Segmented Array 45
Chapter 2 Performance Figures of D/A-Converters 48
2.1 Static Accuracy 48
2.1.1 Gain and Offset Error 48
2.1.2 Differential Nonlinearity 49
2.1.3 Integral Nonlinearity 50
2.2 Dynamic Performance 51
2.2.1 Harmonic Distortion 51
2.2.2 Intermodulation Distortion 52
2.2.3 Spurious Free Dynamic Range 53
2.2.4 Dynamic Range 54
2.2.5 Multitone Linearity 55
Missing Tone Power Ratio 56
Missing Band Power Ratio 57
2.3 Noise Performance 58
2.3.1 Quantization ``Noise'' 58
Nyquist-rate Converter 59
Noiseshaped Converter 60
2.3.2 Circuit Noise 61
2.3.3 Jitter Noise 69
NRZ D/A-Converter 72
Return-to-Zero DAC 74
Sampling Jitter in Multitone Systems 78
Experimental verification 81
Chapter 3 Static Linearity 86
3.1 Limitations for the Static Linearity 86
3.1.1 Matching of Current Sources 87
3.1.2 Statistical Description of the INL 88
3.1.3 Statistical Description of the DNL 89
3.1.4 Minimum Area Requirements 91
3.1.5 Code-Dependent Output Impedance 97
3.2 Dynamic Element Matching Techniques 101
3.2.1 Clocked Level Averaging 103
3.2.2 Data-Weighted Averaging 104
3.2.3 Other DEM Techniques 105
3.3 Current Source Calibration 107
3.3.1 Factory Trimming 108
3.3.2 Self-calibration 109
3.3.3 Local Calibration DAC 111
3.3.4 Global Calibration DAC 112
3.3.5 Trimmable Floating Current Source 113
3.3.6 Dynamic Current Calibration 114
Chapter 4 Dynamic Linearity 119
4.1 Limitations for the Dynamic Linearity 119
4.1.1 Frequency-Dependent Output Impedance 119
4.1.2 A Generalized Switching Error Model 124
4.1.3 Switching Transition Mismatch 129
4.1.4 Charge Sharing at the Switching Node 133
4.1.5 A SPICE-Simulation Example 138
4.1.6 Other Nonlinear Effects 140
4.2 Methods to Improve the Dynamic Performance 140
4.2.1 Current Switch with Reduced Gate Voltage Swing 141
4.2.2 Source Node Bootstrapping 144
4.2.3 Source Node Isolation 145
4.2.4 Differential Quad Switching 146
4.2.5 Constant Digital Activity 147
4.2.6 Return-to-Zero and Track/Attenuate 148
4.2.7 Double Return-to-Zero 150
4.2.8 Full-Clock Interleaved Current Cells 151
Chapter 5 Noiseshaped D/A-Converters 154
5.1 A 14-bit Low-Power D/A-Converter 154
5.1.1 Converter Architecture 155
5.1.2 DEM Selection 156
5.1.3 Unit Current Cell 157
5.1.4 Low-Noise Biasing 159
5.1.5 Output Stage 159
5.1.6 Layout 160
5.1.7 Experimental Results 162
5.2 A 12-Bit/14-Bit Multistandard DAC 165
5.2.1 Low-OSR Noiseshaper 166
5.2.2 Interleaved Data Weighted Averaging 168
5.2.3 Converter Architecture 171
5.2.4 Current-Cell Design 173
5.2.5 Low-Noise Biasing 174
5.2.6 Output Stage Design 176
5.2.7 Layout 178
5.2.8 Experimental Results 180
5.3 Literature Comparison of Noiseshaped DACs 184
Chapter 6 Advanced Current Calibration 187
6.1 A Self-calibrated 13-Bit 100–200MS/s D/A-Converter 188
6.1.1 Converter Architecture 188
6.1.2 Trimmable PMOS Current Cell 189
6.1.3 Segmented Background Calibration 192
6.1.4 Randomized Calibration Cycle 196
6.1.5 Layout 200
6.1.6 Experimental Results 201
Noiseshaped Converter Mode 207
6.2 A 13-Bit 130–300MS/s DAC with Active Output Stage 210
6.2.1 Converter Architecture 211
6.2.2 The Current Cells 212
6.2.3 Direct Segment Calibration 214
6.2.4 Programmable Biasing 218
6.2.5 Push-Pull Operational Amplifier 219
6.2.6 Output Stage Optimization 220
6.2.7 Layout 222
6.2.8 Experimental Results 223
6.3 A Figure-of-Merit for Nyquist D/A-Converters 231
Chapter 7 Conclusion and Outlook 236
7.1 Conclusions 236
7.2 Outlook 238
Appendix A DAC Bias Noise Model 241
A.1 Bias Noise Model Without 1/f-Noise 241
A.2 DMT Synthesis with Correlated 1/f-Noise 243
A.3 Maximum SNR Limited by Correlated Bias Noise 246
Appendix B Jitter Noise 248
B.1 Sampling Jitter Model 248
B.2 Non Return-to-Zero DAC 250
B.3 Return-to-Zero DAC 252
B.4 Jitter in Multitone Systems 255
Appendix C Code-Dependent Output Resistance 260
C.1 Single-Ended Converter 260
C.2 Fully Differential Converter 262
Appendix D Switching errors 265
D.1 Generalized Switching Error Model 265
D.2 Switching Transition Mismatch with Thermometer Coding 267
D.3 Switching Transition Mismatch with Data Weighted Averaging 269
D.4 Charge Sharing with Thermometer Coding 271
D.5 Charge Sharing with Data Weighted Averaging 272
D.6 Output Voltage Feedthrough Factor 273
D.6.1 Single-Polarity DAC with Passive Termination 274
D.6.2 Dual-Polarity DAC with Active Termination 276
D.7 Third-Order Two-Tone Nonlinearity 277
About the Author 282
References 284
Index 293