CMOS Receiver Front-ends for Gigabit Short-Range Optical Communications (eBook)

Preface 4
Contents 7
Symbols 10
Acronyms 13
1 Introduction 16
1.1…Optical Communications 17
1.1.1 A Look at History 17
1.1.2 Emerging Applications 19
1.1.2.1 Short-Haul NetworksShort-haul networks 20
1.1.2.2 In-Car Fiber-Optic NetworksIn-car fiber-optic networks 21
1.1.2.3 High-Speed Optical Interconnects 21
1.1.3 Comparison Between Communication Links 22
1.1.4 Optical Link Architecture 24
1.2…CMOS TechnologyCMOS technology 25
1.3…State of the Art 27
1.4…Outline of the Work 28
References 31
2 Optical Signal Transmission 33
2.1…Data Signal 33
2.1.1 Time Domain 34
2.1.2 Frequency Domain 37
2.1.3 Pseudorandom Bit Sequence 40
2.2…Optical Channels 42
2.2.1 Fundamentals of Optical Fibers 42
2.2.1.1 Single Mode vs. Multi Mode Optical Fiber 45
2.2.1.2 Step Index vs. Graded Index Optical Fiber 45
2.2.2 Glass Optical Fibers 46
2.2.3 Plastic Optical Fibers 47
2.3…Transceiver Front-End 48
2.3.1 Serializer 48
2.3.2 Laser DiodeLaser Diode 50
2.3.3 PhotodiodePhotodiode and Front-End 53
2.3.4 Deserializer 56
2.4…Key Parameters 57
2.4.1 Eye Diagram 58
2.4.2 Bit Error Ratio 58
2.4.3 SensitivitySensitivity 62
2.4.3.1 Extinction RatioExtinction Ratio 63
2.4.3.2 Decision Offset 65
2.4.3.3 Inter-Symbol Interference 67
2.4.3.4 Lower Cut-off Frequency 68
2.4.4 Dynamic RangeDynamic Range 71
2.5…Conclusions 71
3 TransimpedanceTransimpedance Amplifier 74
3.1…Optimum BandwidthBandwidth 75
3.2…Shunt Feedback TIA 77
3.3…Review of TIA Topologies 81
3.4…Input Dynamic Range Extension Techniques 82
3.4.1 Variable Feedback Resistor 83
3.4.2 Compression Technique 85
3.4.2.1 Duty Cycle Distortion 86
3.4.2.2 Logarithmical Compression Model 87
3.5…Proposed TIA Design 88
3.5.1 180 nm TransimpedanceTransimpedance Amplifier Architecture 89
3.5.1.1 TransimpedanceTransimpedanceGain Variation 90
3.5.2 90 nm TransimpedanceTransimpedance Amplifier Architecture 92
3.6…Experimental Verification 93
3.6.1 90 nm TIA 94
3.6.1.1 Optical Characterization 95
3.6.2 180 nm TIA 100
3.6.2.1 Optical Characterization 102
3.6.2.2 Electrical Characterization 104
3.7…Conclusions 106
References 110
4 Post-Amplifier 112
4.1…Amplifier Core 113
4.1.1 Multistage Structure 113
4.1.2 Broadband Techniques 115
4.1.2.1 Inter-stage Buffering 115
4.1.2.2 Inverse Scaling 116
4.1.2.3 Negative Capacitances 117
4.1.2.4 Zero-Pole Cancellation 118
4.2…Automatic Gain Control 118
4.2.1 Linear-in-dB Gain Distribution 120
4.2.2 Discrete Gain Distribution 121
4.3…Offset Compensation 123
4.4…Proposed AGC Design 126
4.4.1 Amplifier Core Architecture 126
4.4.1.1 Differential Gain Stage 126
4.4.1.2 Fourth Stage 127
4.4.1.3 Multi-Stage Amplifier Architecture 128
4.4.1.4 Bandwidth Enhancement 129
4.4.2 Programmable Gain 131
4.4.3 AGC Loop 136
4.4.3.1 Proposed State Diagram 136
4.4.3.2 AGC Loop Implementation 137
4.4.3.3 Shift Register 138
4.4.3.4 Peak Detector 139
4.4.3.5 Comparators 141
4.4.4 Offset Compensation Loop 142
4.5…Experimental Verification 145
4.5.1 PGA Implementation 145
4.5.2 AGC Implementation 146
4.5.3 PCB Characterization 148
4.5.4 On-Wafer Characterization 150
4.5.4.1 Programmable Gain Amplifier Results 151
4.5.4.2 AGC Post-Amplifier Results 154
4.6…Conclusions 155
References 157
5 POF Receiver 160
5.1…Plastic Optical Fiber 160
5.1.1 Optical Fiber Bandwidth 161
5.1.2 Bandwidth-Length Dependency 161
5.2…EqualizationEqualization 162
5.2.1 EqualizationEqualization Techniques 162
5.2.2 Adaptive EqualizationEqualization 164
5.3…Receiver Architecture 166
5.3.1 Preamplifier with PD Monitor 167
5.3.2 Adaptive Equalizer Implementation 169
5.3.2.1 Voltage-Controlled Equalizer 170
5.3.2.2 Low-Pass Filter 171
5.3.2.3 Power Error Detector 173
5.3.3 Post-Amplifier and Output Driver 175
5.4…Experimental Verification 176
5.4.1 Receiver Implementation 177
5.4.2 Results 177
5.5…Conclusions 182
References 184
6 Conclusions 186
6.1…General Conclusions 186
6.2…Further Research Directions 188
Appendix 190
Measurement Considerations 190
S ParametersS parameters 190
CalibrationCalibration 192
De-EmbeddingDe-embedding 194
PRBS GeneratorPRBS Generator 195
Technological Parameters 198
UMC 0.18 microm Mixed-Mode/RF CMOS Process 199
UMC 90 nm Logic and Mixed-Mode Process 200
References 201
Index 202