Design Recipes for FPGAs: Using Verilog and VHDL (eBook)

Front cover 1
Design Recipes for FPGAs 4
Copyright page 5
Contents 8
Acknowledgements 18
Preface 20
List of Figures 22
Part 1 Overview 24
Chapter 1 Introduction 26
Why FPGAs? 26
Chapter 2 An FPGA Primer 28
Introduction 28
FPGA evolution 28
Programmable logic devices 29
Field programmable gate arrays 29
FPGA design techniques 33
Design constraints using FPGAs 33
Summary 33
Chapter 3 A VHDL Primer The Essentials 34
Introduction 34
Entity: model interface 35
Architecture: model behavior 37
Process: basic functional unit in VHDL 39
Basic variable types and operators 40
Decisions and loops 43
Hierarchical design 46
Debugging models 49
Basic data types 49
Summary 51
Chapter 4 Design Automation and Testing for FPGAs 53
Simulation 53
Libraries 56
Synthesis 59
Physical design flow 62
Place and route 63
Timing analysis 63
Design pitfalls 63
VHDL issues for FPGA design 64
Summary 64
Part 2 Applications 66
Chapter 5 Images and High-Speed Processing 68
Introduction 68
The camera link interface 69
Getting started 72
Specifying the interfaces 74
Defining the top level design 74
System block definitions and interfaces 75
The cameralink interface 77
The PC interface 78
Summary 79
Chapter 6 Embedded Processors 80
Introduction 80
A simple embedded processor 80
Soft core processors on an FPGA 101
Summary 102
Part 3 Designer's Toolbox 104
Chapter 7 Serial Communications 106
Introduction 106
Manchester encoding and decoding 106
NRZ coding and decoding 110
NRZI coding and decoding 110
RS-232 112
Universal Serial Bus 116
Summary 119
Chapter 8 Digital Filters 120
Introduction 120
Converting S-domain to Z-domain 121
Implementing Z-domain functions in VHDL 123
Basic low pass filter model 128
FIR filters 131
IIR filters 132
Summary 132
Chapter 9 Secure Systems 133
Introduction to block ciphers 133
Feistel lattice structures 133
The Data Encryption Standard 136
Advanced Encryption Standard 144
Implementing AES in VHDL 149
Summary 162
Chapter 10 Memory 163
Introduction 163
Modeling memory in VHDL 164
Read Only Memory 164
Random Access Memory 166
Synchronous RAM 168
FLASH memory 170
Summary 172
Chapter 11 PS/2 Mouse Interface 173
Introduction 173
PS/2 mouse basics 173
PS/2 mouse commands 174
PS/2 mouse data packets 174
PS/2 operation modes 174
PS/2 mouse with wheel 175
Basic PS/2 mouse handler VHDL 175
Modified PS/2 mouse handler VHDL 176
Summary 178
Chapter 12 PS/2 Keyboard Interface 179
Introduction 179
PS/2 keyboard basics 179
PS/2 keyboard commands 180
PS/2 keyboard data packets 180
PS/2 keyboard operation modes 180
Summary 183
Chapter 13 A Simple VGA Interface 184
Introduction 184
Basic pixel timing 185
Image handling 185
VGA interface VHDL 185
Horizontal sync 187
Vertical sync 188
Horizontal and vertical blanking pulses 189
Calculating the correct pixel data 190
Summary 191
Part 4 Optimizing Designs 192
Chapter 14 Synthesis 194
Introduction 194
VHDL supported in RTL synthesis 195
Some interesting cases where synthesis may fail 197
What is being synthesized? 198
Summary 201
Chapter 15 Behavioral Modeling in VHDL 202
Introduction 202
How to go from RTL to behavioral VHDL 202
Summary 206
Chapter 16 Design Optimization 207
Introduction 207
Techniques for logic optimization 207
Improving performance 209
Critical path analysis 210
Summary 211
Chapter 17 VHDL-AMS 212
Introduction 212
Introduction to VHDL-AMS 213
Analog pins: TERMINALS 214
Mixed-domain modeling 215
Analog variables: quantities 216
Simultaneous equations in VHDL-AMS 217
A VHDL-AMS example 217
Differential equations in VHDL-AMS 219
Mixed-signal modeling with VHDL-AMS 220
A basic switch model 224
Basic VHDL-AMS comparator model 225
Multiple domain modeling 227
Summary 228
Chapter 18 Design Optimization Example: DES 230
Introduction 230
The DES 230
Moods 231
Initial design 231
Initial synthesis 237
Optimizing the data path 238
Final optimization 241
Results 242
Triple DES 242
Comparing the approaches 246
Summary 247
Part 5 Fundamental Techniques 248
Chapter 19 Counters 250
Introduction 250
Basic binary counter 250
Synthesized simple binary counter 253
Shift register 256
The Johnson counter 257
BCD counter 259
Summary 260
Chapter 20 Latches, Flip-Flops and Registers 261
Introduction 261
Latches 261
Flip-flops 263
Registers 266
Summary 267
Chapter 21 Serial to Parallel & Parallel to Serial Conversion
Serial to Parallel Conversion 268
Parallel to Serial Conversion 269
Summary 270
Chapter 22 ALU Functions 271
Introduction 271
Logic functions 271
1-bit adder 274
Structural n-bit addition 275
Configurable n-bit addition 276
Twos complement 277
Summary 280
Chapter 23 Decoders and Multiplexers 281
Decoders 281
Multiplexers 283
Summary 285
Chapter 24 Finite State Machines in VHDL 286
Introduction 286
State transition diagrams 286
Implementing FSM in VHDL 287
Summary 288
Chapter 25 Fixed Point Arithmetic in VHDL 289
Introduction 289
Basic fixed point types 291
Fixed point functions 292
Testing the fixed point function 295
Summary 297
Chapter 26 Binary Multiplication 298
Introduction 298
Basic binary multiplication 298
VHDL unsigned multiplier 299
Synthesis of the multiplication function 302
'Simple' multiplication 303
Summary 305
Chapter 27 Bibliography 306
Introduction 306
Useful texts for VHDL 306
Useful Texts for FPGAs 307
General Digital Design Books 307
Index 310
A 310
B 310
C 310
D 310
E 310
F 310
L 310
M 311
P 311
R 311
S 311
V 311
Z 312