Hardware/Firmware Interface Design (eBook)

Front Cover 1
Title Page 2
Copyright Page 3
Table of Contents 4
Preface 11
Chapter 1: Introduction 18
1.1. What Is the Hardware/Firmware Interface? 19
1.1.1. What Are Hardware, Chips, and Blocks? 19
1.1.2. What Are Firmware and Device Drivers? 23
1.2. What Is a Best Practice? 24
1.2.1. What Is a Principle? 26
1.2.2. Benefits of Principles and Practices 27
1.3. “First Time Right” Also Means … 27
1.3.1. Easier to Program 28
1.3.2. Easier to Debug 28
1.3.3. Easier to Work around Defects 29
1.4. Target Audience 30
1.4.1. Hardware Engineers 30
1.4.2. Firmware Engineers 30
1.4.3. This Book in a University Setting 31
1.5. Project Life Cycle 31
1.6. Case Study 32
1.6.1. Monochrome Video Block in the Unity ASIC 32
1.6.2. A Case Study of a Good Example? 34
1.7. Summary 34
References 35
Chapter 2: Principles 36
2.1. Seven Principles of Hardware/Firmware Interface Design 36
2.1.1. Collaborate on the Design 37
2.1.2. Set and Adhere to Standards 38
2.1.3. Balance the Load 40
2.1.4. Design for Compatibility 42
2.1.5. Anticipate the Impacts 43
2.1.6. Design for Contingencies 44
2.1.7. Plan Ahead 46
2.2. Summary 47
Chapter 3: Collaboration 48
3.1. First Steps 48
3.1.1. Roles 48
3.1.2. Kick-off Activities 51
3.2. Formal Collaboration 52
3.2.1. Regular Meetings 52
3.2.2. Initial Firmware Support 54
3.2.3. Co-Development Techniques 55
3.2.4. End-Game Hardware Support 57
3.2.5. Documentation 58
3.3. Informal Collaboration 61
3.3.1. Formal Organizational Structure 61
3.3.2. Hardware Engineers’ Initiative 62
3.3.3. Firmware Engineers’ Initiative 63
3.3.4. Collaborative Problem Solving 64
3.4. Summary 65
3.4.1. Supporting Principles 66
References 66
Chapter 4: Planning 68
4.1. Industry Standards 68
4.1.1. Existing Standards 69
4.1.2. Implementing the Standard 70
4.1.3. Derivations or New Creations 72
4.2. Common Version 73
4.3. Compatibility 75
4.3.1. Range of Backward and Forward Compatibility 76
4.3.2. Combinations of Old vs. New 77
4.4. Defects 78
4.4.1. Document Defects 78
4.4.2. Fix Defects 80
4.4.3. Test Plan to Look for Defects 82
4.5. Analysis 83
4.5.1. Shared Pins 83
4.5.2. Buffer Management 84
4.5.3. Hardware/Firmware Interactions 84
4.5.4. Analyzing Third-Party IP 86
4.6. Postmortem 87
4.7. Summary 88
4.7.1. Supporting Principles 89
Chapter 5: Documentation 90
5.1. Types 91
5.1.1. Level and Types of Documentation 91
5.1.2. Chip-Level vs.Block-Level Documentation 92
5.1.3. Supported vs. Unsupported Documentation 94
5.2. Document Management 96
5.2.1. Document Standards 96
5.2.2. When to Write 97
5.2.3. Accuracy 98
5.3. Reviews 100
5.3.1. When to Review 100
5.3.2. Tracking Documentation Changes 101
5.3.3. Firmware Engineers’ Responsibilities Regarding Reviews 102
5.4. Content 104
5.4.1. General Content 104
5.4.2. Sample Document Template 105
5.4.3. History 106
5.4.4. Features and Assumptions 108
5.4.5. Reference and Tutorial 109
5.4.6. Glossary and Errata 111
5.5. Registers 112
5.5.1. Document Registers 112
5.5.2. Register Design Tools 113
5.5.3. Table of Registers 117
5.5.4. Register Details and Description 118
5.6. Bits 120
5.6.1. Register Map Format 120
5.6.2. Bit Positions, Types, and Defaults 121
5.6.3. Bit Descriptions 123
5.6.4. Abort Impact 123
5.6.5. Test and Debug Bits 124
5.7. Interrupts 125
5.7.1. Edge- vs. Level-Triggered 125
5.7.2. Enabling and Acknowledging Interrupts 126
5.7.3. Interrupts Not Quite Done 127
5.7.4. Interrupts Repeating without Intervention 127
5.8. Time 128
5.8.1. Ranges of Time 128
5.8.2. Unit of Time 130
5.9. Errors 131
5.9.1. Two Types of Errors 132
5.9.2. Copious Information about the Errors 133
5.9.3. State of the Block after an Error 134
5.9.4. Firmware Steps to Recover 135
5.10. Information 136
5.10.1. Illegal Configuration 136
5.10.2. State Machines 136
5.10.3. How to Abort 137
5.11. Summary 138
5.11.1. Supporting Principles 139
Chapter 6: Superblock 140
6.1. Benefits of a Superblock 140
6.1.1. The Block’s Entourage 141
6.1.2. Reasons for Having Unused Logic 141
6.1.3. Reasons against Having Unused Logic 146
6.2. Consolidation 148
6.2.1. Make a Superblock 148
6.2.2. Make a Supermodule 150
6.2.3. Evolutionary Design 150
6.2.4. Add Future Features 152
6.2.5. Superblock Version Number 154
6.3. I/O Signals 154
6.4. Parameterization 156
6.4.1. Reducing the Silicon Space 156
6.4.2. Minimizing Parameterization Risks 157
6.4.3. Parameterization Information for Firmware 159
6.4.4. Optional vs. Fixed Registers and Bits 162
6.5. Summary 163
6.5.1. Supporting Principles 164
Reference 164
Chapter 7: Design 166
7.1. Event Notification 166
7.1.1. No Indication 167
7.1.2. Timed Delay 168
7.1.3. Status Bit 170
7.1.4. Interrupts 172
7.2. Performance 174
7.2.1. Increasing the Buffer 175
7.2.2. Working Ahead 176
7.2.3. Tuning 177
7.2.4. Margins 178
7.3. Power-On 178
7.3.1. Power-On Interaction 178
7.3.2. Power-On State of I/O Lines 180
7.3.3. Block-Level Power Control 180
7.4. Communication and Control 181
7.4.1. Error Information 181
7.4.2. DMA Features 181
7.4.3. Sharing I/O Pins 183
7.4.4. Hiding Implementation Details 184
7.5. Summary 186
7.5.1. Supporting Principles 187
Chapter 8: Registers 188
8.1. Addressing 189
8.1.1. Processor Access 189
8.1.2. Chip Base Addresses 192
8.1.3. Block Offset and Base Addresses 193
8.1.4. Register Offset Addresses 195
8.1.5. Sub-Blocks 196
8.1.6. Bursting 196
8.1.7. Unused Address Locations 197
8.1.8. Changes in the Next Chip 198
8.2. Bit Assignment 200
8.2.1. Assigning Bit Positions 200
8.2.2. Multi-Bit Fields 202
8.2.3. Multi-Register Fields 204
8.2.4. Unused Bit Positions 205
8.2.5. Changes in the Next Revision 206
8.2.6. Bit Types 209
8.2.7. Bit Types in Registers 212
8.2.8. Grouping by Operational Mode 214
8.2.9. Multiple Instantiations of a Block 215
8.3. Data Types 216
8.3.1. Integers 217
8.3.2. Real Numbers 218
8.3.3. Pointers 222
8.3.4. Constants 224
8.4. Hardware Identification 224
8.4.1. Chip ID and Version 225
8.4.2. Block ID and Version 226
8.5. Communication and Control 227
8.5.1. Necessary Information 227
8.5.2. Queuing Tasks in the Block 228
8.5.3. Coherent Register Contents 233
8.5.4. Atomic Register Access 234
8.6. Summary 238
8.6.1. Supporting Principles 239
Chapter 9: Interrupts 240
9.1. Design 241
9.1.1. An Interrupt Supermodule 241
9.1.2. Hierarchical Interrupt Structure 243
9.1.3. Interrupt Sharing 245
9.1.4. Source Signal Integrity 247
9.1.5. Types of Interrupt Triggers 248
9.2. Pending Register 253
9.2.1. Acknowledging an Interrupt 253
9.2.2. Order of Interrupt Positions 256
9.3. Enable Register 257
9.3.1. A 1 Enables the Interrupt 258
9.3.2. Enable Controls Interrupt 258
9.3.3. Default Settings for Enable 260
9.4. Optional Registers 260
9.4.1. Source Status Register 260
9.4.2. Post Register 262
9.4.3. Atomic Enable/Disable Registers 262
9.4.4. Masked Register 263
9.4.5. Instantiation Register 263
9.4.6. Addresses of Optional Registers 264
9.5. Interrupt Module Review 265
9.5.1. Interrupt Channels 266
9.5.2. Interrupt Module 268
9.5.3. External Connections 269
9.6. Triggering on Both Edges 270
9.6.1. Use Two Interrupt Channels 270
9.6.2. Channel Positions of Leading and Trailing Interrupts 272
9.7. Using the Interrupt Module 274
9.7.1. When to Allocate an Interrupt Channel 274
9.7.2. Repeated Interrupts 276
9.7.3. Address Mapping 276
9.8. Summary 277
9.8.1. Supporting Principles 278
Chapter 10: Aborts, etc. 280
10.1. Definitions 280
10.2. Halts 282
10.3. Resets 283
10.4. Aborts 285
10.4.1. The Need for Aborts 285
10.4.2. Firmware’s Interaction with Aborts 287
10.4.3. Abort Behavior 289
10.4.4. Abort Interactions between Blocks 291
10.5. Summary 292
10.5.1. Supporting Principles 293
Chapter 11: Hooks 294
11.1. Designing for Hooks 295
11.1.1. What Hooks to Add 296
11.1.2. Adding Registers 296
11.1.3. Looking for Potential Problem Areas 297
11.1.4. Removing Workarounds 297
11.2. Peek… 298
11.2.1. Internal Registers 298
11.2.2. Signals 299
11.2.3. Memory 300
11.2.4. State Machines 302
11.3. …And Poke 304
11.3.1. Destructive Reads and Writes 304
11.3.2. Input and Output Signals 305
11.3.3. Overwriting Registers 306
11.4. Monitor 306
11.4.1. Event Tracking 306
11.4.2. Timers 308
11.4.3. Data Watching 309
11.5. More Hooks 310
11.5.1. Bypass Paths 310
11.5.2. Extra Resources for Test and Debug 312
11.5.3. Dedicated Processor 314
11.6. Summary 315
11.6.1. Supporting Principles 316
Chapter 12: Conclusion 318
12.1. Key Points 318
12.2. Benefits 319
12.3. Seven Principles of Hardware/Firmware Interface Design 319
12.4. It Finally Works! Let’s Ship It! 320
Appendix A: Best Practices 324
Appendix B: Bicycle Controller Specification 344
Appendix D: Glossary 362
Index 366