Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (eBook)
XXI, 328 Seiten
Springer US (Verlag)
978-0-387-46547-0 (ISBN)
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.
Dedication 6
Contents 7
Preface 12
Foreword 15
Foreword for the First Edition 17
Acknowledgements 19
Chapter 1 INTRODUCTION 20
1. EVOLUTION OF CMOS TECHNOLOGY 20
2. THE TEST COMPLEXITY 24
3. QUALITY AND RELIABILITY AWARENESS 28
4. BUILDING QUALITY AND RELIABILITY 30
5. OBJECTIVES OF THIS BOOK 34
6. BOOK ORGANIZATION 35
References 37
Chapter 2 FUNCTIONAL AND PARAMETRIC DEFECT MODELS 42
1. BRIEF CLASSIFICATION OF DEFECTS 42
1.1 Defect-Fault Relationship 45
2. INDUCTIVE FAULT ANALYSIS 47
2.1 IC Design and Layout Related Defect Sensitivity 48
2.2 Defect Sensitive Design 48
2.3 Basic Concepts of IFA 49
3. PARAMETRIC DEFECT AND FAULT MODELS 51
3.1 Threshold Voltage Mismatch (.Vt) Fault Modeling 51
3.2 Sources of Threshold Voltage Variability 52
3.3 Leakage Current due to Vt Mismatch Mismatch 53
3.4 Delay in Parallel-connected Networks 58
3.5 Delay Variation Model with with for Parallel Transistor Networks 60
3.6 Spot Defect Statistics: Resistive Opens 64
4. FUNCTIONAL DEFECT MODELS 69
4.1 Critical Areas 72
4.2 Defect Statistics 73
4.3 Average Probability of Failure of Long Interconnects 77
4.4 Average Critical Area of N Conductors 80
5. CONCLUSIONS 83
References 83
Chapter 3 DIGITAL CMOS FAULT MODELING 87
1. OBJECTIVES OF FAULT MODELING 87
2. LEVELS OF TESTING 89
3. LEVELS OF FAULT MODELING 91
3.1 Logic Level Fault Modeling 91
3.2 Transistor Level Fault Modeling 99
3.3 Layout Level Fault Modeling 108
3.4 Function Level Fault Modeling 109
3.5 Delay Fault Models 110
3.6 Leakage Fault Model 115
3.7 Temporary Faults 116
4. CONCLUSIONS 120
References 120
Chapter 4 DEFECTS IN LOGIC CIRCUITS AND THEIR TEST IMPLICATIONS 129
1. INTRODUCTION 129
2. STUCK-AT FAULTS AND MANUFACTURING DEFECTS 131
2.1 Study by Galiay, Crouzet, and Vergniault 132
2.2 Study by Banerjee and Abraham 133
2.3 Study by Maly, Ferguson and Shen 138
2.4 Gate Oxide Shorts: Study by Hawkins and Soden 141
3. IFA EXPERIMENTS ON STANDARD CELLS 144
4. IDDQ VERSUS VOLTAGE TESTING 148
5. DEFECTS IN SEQUENTIAL CIRCUITS 151
5.1 Undetected Defects 153
5.2 Defect Detection Technique 155
5.3 IDDQ Testable Flip- flop 157
5.4 Defects and Scan Chains 157
6. DEFECT CLASSES AND THEIR TESTING 161
7. APPLICATION OF IFA IN NANO-METRIC TECHNOLOGIES 161
8. CONCLUSIONS 164
References 165
Chapter 5 TESTING DEFECTS AND PARAMETRIC VARIATIONS IN RAMS 169
1. INTRODUCTION 169
2. TRADITIONAL RAM FAULT MODELS 171
2.1 Stuck-at Fault Model 171
2.2 Coupling Fault Model 172
2.3 Pattern Sensitivity Fault Model 172
3. DEFECT BASED RAM FAULT MODEL DEVELOPMENT 173
3.1 Defect based SRAM Fault Models and Test Algorithms 173
3.2 Subsequent Defect-oriented SRAM Test Development 178
3.3 Defect based DRAM Fault Models and Test Algorithms 181
3.4 TCAM Fault Models and Test Algorithms 194
4. ADDRESS DECODER DEFECTS 203
4.1 Early Work on Address Decoder Faults 205
4.2 Technological Differences 205
4.3 Failure and Analysis 207
4.4 Why Non-detection by March Tests? 210
4.5 Address Decoder Open Defects 211
4.6 Supplementary Test Algorithm 213
4.7 Testability Techniques for Decoder Open Defects 215
4.8 Recent Work on Address Decoder Defects 218
5. PARAMETRIC TESTING OF SRAMS 218
5.1 SRAM Cell and SNM 221
5.2 Process Variation and SNM 225
5.3 Manufacturing Defects and SNM 227
5.4 Weak Cell Fault Model 228
5.5 DFT Techniques to Detect Weak Cells 229
6. IDDQ BASED RAM TESTING 233
7. CONCLUSIONS 233
References 235
Chapter 6 DEFECT- ORIENTED ANALOG TESTING 242
1. INTRODUCTION 243
2. ANALOG TEST COMPLEXITY 244
3. PREVIOUS WORK 245
3.1 Estimation Method 245
3.2 Topological Method 245
3.3 Taxonomical Method 247
4. DEFECT BASED REALISTIC FAULT DICTIONARY 247
4.1 Implementation 251
5. A CASE STUDY 257
5.1 Fault Matrix Generation 257
5.2 Stimuli Matrix 259
5.3 Simulation Results 260
5.4 Silicon Results 261
5.5 Observations and Analysis 265
5.6 IFA: Strengths and Weaknesses 266
6. INPUT STIMULI GENERATION 268
6.1 Power Supply Ramp Input Test Stimuli 269
6.2 Amplifier Specs 271
6.3 Structural vs. Functional Fault Coverage 276
6.4 Experimental Results 281
7. IFA BASED FAULT GRADING AND DfT FOR ANALOG CIRCUITS 285
7.1 A/D Converter Testing 285
7.2 Description of the Experiment 286
7.3 Fault Simulation Issues 287
7.4 Fault Simulation Results 289
8. HIGH LEVEL ANALOG FAULT MODELS 295
9. CONCLUSIONS 298
References 301
Chapter 7 YIELD ENGINEERING 305
1. MATHEMATICAL MODELS FOR YIELD PREDICTION 305
1.1 Layout Oriented Yield Prediction 316
2. YIELD ENGINEERING 317
3. ECONOMICS AND YIELD FORECASTING 322
4. CONCLUSIONS 328
References 329
Chapter 8 CONCLUSION 332
1. TEST AND YIELD ENGINEERING COMPLEXITY IN NANO- METRIC TECHNOLOGIES 332
2. ROLE OF DEFECT-ORIENTED TESTING 335
2.1 Strengths of Defect-oriented Testing 335
2.2 Limitations of Defect-oriented Testing 336
3. FUTURE DIRECTIONS 336
References 338
Index 340
| Erscheint lt. Verlag | 4.6.2007 |
|---|---|
| Reihe/Serie | Frontiers in Electronic Testing | Frontiers in Electronic Testing |
| Zusatzinfo | XXI, 328 p. |
| Verlagsort | New York |
| Sprache | englisch |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| Technik ► Nachrichtentechnik | |
| Schlagworte | CMOS • defects • DFM • DSM • Integrated circuit • Logic • RAM • SRAM • Testing • VLSI • yield |
| ISBN-10 | 0-387-46547-2 / 0387465472 |
| ISBN-13 | 978-0-387-46547-0 / 9780387465470 |
| Haben Sie eine Frage zum Produkt? |
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