A Roadmap for Formal Property Verification (eBook)
XIV, 252 Seiten
Springer Netherland (Verlag)
978-1-4020-4758-9 (ISBN)
Integrating formal property verification (FPV) into an existing design process raises several interesting questions. This book develops the answers to these questions and fits them into a roadmap for formal property verification - a roadmap that shows how to glue FPV technology into the traditional validation flow. The book explores the key issues in this powerful technology through simple examples that mostly require no background on formal methods.
The author leads the Formal Verification Group at the Indian Institute of Technology, Kharagpur (http://www.facweb.iitkgp.ernet.in/-pallab/forverif.html). He has collaborations with leading companies, including Intel, Sun Microsystems, Synopsys, Texas Instruments, National Semiconductors, General Motors, Interra Systems and Virtio Corp, on developing formal methods for design verification. The author is a senior member of IEEE.
Integrating formal property verification (FPV) into an existing design process raises several interesting questions. Have I written enough properties? Have I written a consistent set of properties? What should I do when the FPV tool runs into capacity issues? This book develops the answers to these questions and fits them into a roadmap for formal property verification - a roadmap that shows how to glue FPV technology into the traditional validation flow. A Roadmap for Formal Property Verification explores the key issues in this powerful technology through simple examples - you do not need any background on formal methods to read most parts of this book.
The author leads the Formal Verification Group at the Indian Institute of Technology, Kharagpur (http://www.facweb.iitkgp.ernet.in/~pallab/forverif.html). He has collaborations with leading companies, including Intel, Sun Microsystems, Synopsys, Texas Instruments, National Semiconductors, General Motors, Interra Systems and Virtio Corp, on developing formal methods for design verification. The author is a senior member of IEEE.
1. Introduction. 1.1. Writing our First Formal Specification. 1.2. Is my specification correct? 1.3. Have I written enough properties? 1.4. Property Verification. 1.5. Verification by Specification Refinement. 1.6. The new flow. 2. Languages for Temporal Properties. 2.1. The basic temporal operators. 2.2. Logics for temporal specification. 2.3. System Verilog Assertions. 2.4. Architectural Styles for Assertion IPs. 2.5. Concluding Remarks. 2.6. Bibliographic Notes. 3. How does the property checker work? 3.1. Checkers are state machines! 3.2. The verification strategy. 3.3. Dynamic property verification. 3.4. Formal property verification. 3.5. BDD-based Formal Property Verification. 3.6. SAT-based Formal Property Verification. 3.7. Concluding Remarks. 3.8. Bibliographic Notes. 4. Is my specification consistent? 4.1. Satisfiability and Vacuity. 4.2. Satisfiability is not enough. 4.3. Games with the Environment. 4.4. Methods for Consistency Checking. 4.5. The SpecChecker Tool. 4.6. Concluding Remarks. 4.7. Bibliographic Notes. 5. Have I written enough properties? 5.1. Simulation Coverage Metrics. 5.2. Mutation-based FPV Coverage. 5.3. Structural versus Functional Coverage. 5.4. Fault-based FPV Coverage. 5.5. Concluding Remarks. 5.6. Bibliographic Notes. 6. Design Intent Coverage. 6.1. An Introductory Example. 6.2. The Formal Problem. 6.3. The Intent Coverage Algorithm. 6.4. Soundness of the Intent Coverage Algorithm. 6.5. Multi-property representation of the coverage gap. 6.6. SpecMatcher -- The Intent Coverage Tool. 6.7. Priority Cache Access -- A closer look. 6.8. Concluding Remarks. 6.9.Bibliographic Notes 7. Test Generation Games. 7.1. Constraint Random Test Generation. 7.2. Assertions viewed as Coverage Points! 7.3. Games with the Environment 7.4. Intelligent Test Generation for Property Coverage. 7.5. The Integrated Verification Flow. 7.6. Concluding Remarks. 7.7. BibliographicNotes. 8. A Roadmap for Formal Property Verification. 8.1. Simulation-based Validation Flow. 8.2. Formal Verification Flow. 8.3. The Three Pillars. 8.4. The Integrated Flow. 8.5. Sharing the Task. 8.6. Concluding Remarks. 8.7. Bibliographic Notes. 9. References
| Erscheint lt. Verlag | 19.1.2007 |
|---|---|
| Zusatzinfo | XIV, 252 p. |
| Verlagsort | Dordrecht |
| Sprache | englisch |
| Themenwelt | Informatik ► Weitere Themen ► CAD-Programme |
| Mathematik / Informatik ► Mathematik | |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | algorithms • design intent coverage • Environment • Formal Method • formal specification • Formal Verification • FPV methods • Integrated circuit • metal-oxide-semiconductor transistor • Simulation • single-electron transistor • System Verilog Assertions • Technology • VLSI Design Verification |
| ISBN-10 | 1-4020-4758-4 / 1402047584 |
| ISBN-13 | 978-1-4020-4758-9 / 9781402047589 |
| Haben Sie eine Frage zum Produkt? |
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