Nanoelectronic Circuit Design (eBook)

Nanoelectronic Circuit Design 3
Preface 5
Contents 7
Contributors 9
Introduction to Nanotechnology 13
1 FinFETs 15
2 Carbon Nanotube Devices 17
3 Graphene Nanoribbon Devices 21
4 Nanowire Devices 25
5 Resonant Tunneling Diodes and Quantum Cellular Automata 28
5.1 Resonant Tunneling Diodes 28
5.2 Quantum Cellular Automata 30
6 Conclusions 32
References 32
FinFET Circuit Design 35
1 Introduction 35
1.1 Shorted-Gate and Independent-Gate FinFETs 36
2 Logic Design Using SG/IG-Mode FinFETs 37
2.1 Design of Logic Gates 40
3 Threshold Voltage Control Through Multiple Supply Voltages for Power-Efficient FinFET Interconnects 41
3.1 The Principle of TCMS 43
3.2 Circuit Design Considerations 45
3.2.1 Power Consumption in TCMS Circuits 45
3.2.2 Exploratory Buffer Design for TCMS 45
3.3 Logic Design Using TCMS 46
4 Schmitt Trigger 49
5 Latch Design Using SG/IG-Mode FinFETs 51
5.1 SG-Mode Latch Design 51
5.2 IG-Mode FinFET Latch 52
6 Precharge-Evaluate Logic Circuits 53
6.1 FinFET Domino Logic Circuits with SG-Mode FinFETs 53
6.2 FinFET Domino Logic with IG-Mode FinFETs 55
7 FinFET Layout 56
7.1 Layout Analysis of FinFET Standard Cells (SG/IG-Mode) 57
8 Oriented FinFETs 59
8.1 Library Design Using Oriented FinFETs 61
9 Conclusions 62
References 65
FinFET SRAM Design 67
1 Introduction to Nonplanar SRAM 67
2 Why FinFETs? 68
3 Physics, Theory, and Modeling of FinFET Devices for SRAM Applications 70
3.1 First-Order Poisson Equations 73
3.2 Sub-threshold Slope Tracking 73
3.3 Strong-Inversion Region Charge Tracking 74
4 SRAM Design 77
4.1 SRAM Design Requirements and Functionality Metrics 78
4.1.1 Metric 1: Read Stability 79
4.1.2 Metric 2: Writability 80
5 FinFET Design for SRAM 81
5.1 Example of FinFET Simulation Models Used for SRAM Design 81
5.2 3-D Thermal Modeling of FinFET 83
6 Low-Power, High-Performance 90-nm DG-FinFET SRAM Design 86
6.1 Design Overview 87
6.2 Device Models 87
6.3 Width Quantization 89
6.4 Layout and Surface Orientation: A Brief Overview 89
6.5 Performance 90
6.6 Power 92
6.7 Stability 92
7 A High Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology 93
7.1 Back-Gate Design Overview 93
7.2 Dynamic Bias Generator 95
7.3 Analysis of the FinFET SRAM 95
7.4 8T SRAM Cell 97
8 Low-Power and Stable FinFET SRAM 98
8.1 Design Overview 98
8.2 Leakage Current of Footer Device 100
9 Other Mixed Split/DG Designs 102
9.1 Column-Decoupled Design 103
9.1.1 8T-Decoupled Cell 103
9.1.2 6T-Decoupled Cell 103
References 106
A Hybrid Nano/CMOS Dynamically Reconfigurable System 108
1 Introduction 108
2 Background 111
2.1 NRAMs 111
2.2 MRAMs 112
2.3 PCMs 113
3 Temporal Logic Folding 114
4 Architecture of Nature 116
4.1 The SMB Architecture 117
4.2 Support for Reconfiguration 119
4.3 Parameter Optimization for the SMB Architecture 121
4.3.1 Number of LEs (n1) per MB 121
4.3.2 Number of MBs (n2) per SMB 122
4.3.3 Number of Inputs (m) per LUT 122
4.3.4 Number of Flip-flops (l) per LE 122
4.3.5 Number of Reconfiguration Sets (k) 123
4.3.6 Different Types of Nano RAMs 124
4.4 Interconnect Design 124
5 Power Estimation 128
5.1 Switching Power Estimation 128
5.1.1 Effective Capacitance 129
5.1.2 Switching Activity 129
5.2 Leakage Power 131
6 Motivational Example for NanoMap 131
7 NanoMap: Overview of the Optimization Flow 133
8 Logic Mapping 135
8.1 Plane Separation 135
8.2 Folding Level Computation 136
8.2.1 Delay Minimization 138
Initial Folding Level Selection 138
Folding Level Adjustment 139
8.2.2 Area Minimization 139
Initial Folding Level Selection 140
Folding Level Adjustment 140
8.3 Module Library 140
8.4 RTL Module Partitioning 142
8.5 Force-Directed Scheduling 143
8.5.1 Creation of LUT Computation DG 143
8.5.2 Creation of Register Storage DG 144
8.5.3 Calculation of Forces 146
Self-Force 146
Predecessor and Successor Forces 148
8.5.4 Summary of the FDS Algorithm 149
9 Temporal Clustering 149
10 Temporal Placement and Routing 151
11 Simulation-Based Analysis 153
12 Conclusions 156
References 160
Reliable Circuits Design with Nanowire Arrays 163
1 Introduction 163
2 Fabrication Technologies 163
2.1 Nanowire Fabrication Techniques 164
2.1.1 Bottom-Up Techniques 164
2.1.2 Top-Down Techniques 164
2.2 Crossbar Technologies 165
2.2.1 Crossbars with Bottom-Up Nanowires 165
2.2.2 Nanomold-Based Nanowire Crossbars 166
2.2.3 Crossbar Switches 166
3 Architecture of Nanowire Crossbars 166
3.1 Organization of Nanowire Crossbars 166
3.2 Architectures Based on Nanowire Crossbars 167
3.3 Decoding Nanowires 168
3.3.1 Decoders for Differentiated Nanowires 169
3.3.2 Decoders for Undifferentiated Nanowires 169
4 Decoder Logic Design 170
4.1 Semantic of Multi-valued Logic Addressing 170
4.2 Code Construction 173
4.2.1 Hot Encoding 173
4.2.2 N-ary Reflexive Code 173
4.3 Defect Models 174
4.3.1 Basic Error Model 174
4.3.2 Overall Impact of Variability 175
4.4 Impact of the Encoding Scheme 177
5 Testing Crossbars 179
5.1 Testing Procedure 179
5.2 Perturbative Current Model 181
5.3 Stochastic Current Model 182
5.3.1 Distribution of the Useful Signal 183
5.3.2 Distribution of the Defect-Induced Noise 183
5.3.3 Distribution of the Intrinsic Noise 183
5.4 Test-Aware Design Optimization 184
5.5 Testing Procedure 186
5.6 Perturbative Current Model 187
5.7 Stochastic Current Model 189
5.7.1 Distribution of the Useful Signal 189
5.7.2 Distribution of Defect-Induced Noise 189
5.7.3 Distribution of the Intrinsic Noise 190
5.8 Test-Aware Design Optimization 190
6 Conclusions 192
Exercise 1Delay in a Crossbar 192
Exercise 2Process Optimization 193
References 194
Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs 1
1 Introduction 1
2 Primitives 1
2.1 Single-Walled Carbon Nanotube Bundled Interconnect 1
2.2 Nanowire-Based Crossbar Interconnect 1
3 Modeling of SWCNT Interconnect Bundles 1
4 Replacing Copper by SWCNT Bundle-Based Interconnect 1
4.1 Assumptions and Experimental Setup 1
4.2 Segmentation Experiments 1
4.3 SB/CB Configurations 1
5 Routing Fabric Design Using Crossbar and Molecular Switches 1
5.1 Architecture 1 1
5.2 Architecture 2 1
5.3 Evaluation 1
6 Results 1
7 Related Work 1
8 Conclusions 1
References 1
Nanoscale Application-Specific Integrated Circuits 223
1 Fabric Introduction 223
2 NASIC Building Blocks: Nanowires and xnwFETs 225
2.1 Semiconductor Nanowires 225
2.2 xnwFET Devices 226
2.2.1 Design Motivation and Nanowire-Level Approaches 227
2.2.2 xnwFET Device-Level Design Approaches 228
3 NASIC Circuit Styles 230
3.1 NASICs with Static Ratioed Logic 231
3.2 NASIC Dynamic Circuits and Timing Schemes 232
3.2.1 Sequential Circuits Using Dynamic Circuit Styles 234
3.3 Integrated Device-Circuit Exploration 236
3.3.1 Methodology 236
3.3.2 Control Schemes for the NASIC Fabric 240
4 NASIC Logic Styles 243
5 NASIC Architectures 244
5.1 Wire Streaming Processor 244
5.1.1 Wisp-0 Program Counter 244
5.1.2 Wisp-0 ALU 245
5.2 Nanodevice-Based Programmable Architectures 246
6 Built-in Fault Tolerance 248
6.1 Techniques for Masking Manufacturing Defects 249
6.1.1 Circuit-Level and Structural Redundancy 250
6.1.2 Interleaving Nanowires 251
6.1.3 Integrated Code-Based Error Masking 252
6.1.4 Voting at the Nanoscale 253
6.2 Density Evaluation 255
6.3 Yield Evaluation for WISP-0 257
6.4 Process Variation Mitigation 259
6.4.1 Initial Study on Impact of Redundancy for Masking Delay Faults 260
6.4.2 Design of Fast-Track Techniques 261
6.4.3 Method of Evaluation 262
6.4.4 Fast Track Results 264
7 Discussion on Performance and Power 266
8 Manufacturing 268
8.1 Fabric Choices Targeting Manufacturability 268
8.2 Manufacturing Pathway 269
8.2.1 Nanowire Growth and Alignment 271
8.2.2 Nanowire Grid Functionalization 275
9 Summary and Future Work 275
References 280
Imperfection-Immune Carbon Nanotube VLSI Circuits 284
1 Introduction 285
2 Mis-Positioned-CNT-Immune Logic Design 286
3 Metallic-CNT-Immune CNFET Circuits 295
3.1 ACCNT: Asymmetrically Correlated CNT Technology 295
3.2 VMR: VLSI-Compatible Metallic-CNT Removal 300
4 Probabilistic Analysis of CNFET Circuits 305
5 Conclusion 309
References 311
FPCNA: A Carbon Nanotube-Based Programmable Architecture 313
1 Introduction 314
2 Related Work 314
3 Design Flow 316
4 Nanoelectronic Devices 317
4.1 Carbon Nanotubes 317
4.2 CNT Field-Effect Transistors 319
4.3 CNT Logic 321
4.4 Nram 323
4.5 CNT-Bundle Interconnect 323
4.6 Solid-Electrolyte Nanoswitches 325
5 FPCNA Architecture 325
5.1 CNT-Based LUT 326
5.2 BLE Design 326
5.3 Logic Block Design 328
5.4 High-Level Architecture and Global Routing 330
6 Nanotube LUT Fabrication 332
7 Circuit Characterization 334
7.1 CNFET and CNT-Based LUT Variation 334
7.2 Crossbar Characterization 336
7.3 Timing Block Evaluation 336
8 CAD Flow 337
9 Experimental Results 342
9.1 Experimental Setup 342
9.2 Area Reduction 342
9.3 Performance Gain 344
10 Conclusion and Future Work 349
References 352
Graphene Transistors and Circuits 355
1 Introduction 355
2 Fabrication 356
2.1 Techniques to Open a Band-Gap 357
2.2 Graphene Transistors 360
3 Analog Circuits 362
4 Digital Circuits 365
4.1 GNRFET Digital Circuits 367
4.2 Ambipolar Logic Circuits 368
4.3 Tunneling FETs 369
5 Modeling and Simulation of Graphene Transistors 369
5.1 Charge-Collection Model 370
5.2 Quantum Simulation Techniques 372
5.3 Semi-classical Top-of-the-Barrier Modeling 373
5.4 Semi-classical Model with Tunneling 375
6 Conclusions and Prospects 377
References 378
Study of Performances of Low-k Cu, CNTs, and Optical Interconnects 383
1 Introduction 383
2 Circuit Parameter Modeling 384
2.1 Modeling Parameters for Copper 384
2.1.1 Conventional Interconnect Circuit and Its Performance Limit 387
2.1.2 Interconnect Application of Carbon Nanotubes 388
2.1.3 Modeling Parameters for SWCNT Bundles 389
2.1.4 Secondary Effect of SWCNT Resistance Contacts 394
2.1.5 Graphene Nanoribbon Interconnects 395
2.1.6 Optical Interconnects 396
3 Circuit Modeling 398
4 Local Interconnects: CNT Bundles Versus Cu 400
5 Global and Semiglobal Interconnects 402
5.1 Cu/CNT and Optical Global Wire Circuit Models 402
5.2 Latency and Energy per Bit as a Function of Scaling 403
5.3 Latency, Power Density and Bandwidth Density 406
5.4 Impact of CNT and Optics Technology Improvement 407
References 411
Circuit Design with Resonant Tunneling Diodes 414
1 Introduction 414
2 RTD Fundamentals 415
2.1 Bistable Logic Using RTDs 417
2.2 Noise Margins of RTD-HBT Threshold Logic Gates 419
2.3 Monostable-Bistable Logic Elements 422
2.4 Circuit Examples 426
3 Threshold Logic Synthesis for RTD-Based Devices 428
3.1 Theorems for Threshold Logic 430
3.2 Synthesis Methodology 432
3.3 An Example 437
4 Threshold Logic Testing for RTD-Based Devices 438
4.1 Fault Modeling 438
4.2 Irredundant Threshold Networks and Redundancy Removal 439
4.3 Test Generation 440
References 444
Online Educational Links 444
Circuit Design with Quantum Cellular Automata 445
1 Introduction 445
2 QCA Fundamentals 446
2.1 Basic Logic Gates and Interconnect 447
2.2 Clocking Scheme 449
3 Logic Design with QCA 451
3.1 Hand-Crafted Designs 451
3.2 QCA Logic Synthesis 455
3.3 Tile-Based QCA Design 461
4 Testing of QCA Circuits 463
5 CAD Tools for QCA Design 472
6 Fabrication Technology and Challenges 472
6.1 Metal-Dot QCA 472
6.2 Molelcular QCA 476
7 Future of QCA 479
8 Online Educational Links 480
References 481
Index 482