Three Dimensional System Integration (eBook)

Three Dimensional System Integration 3
Contents 5
Contributors 7
Chapter 1: Introduction to Three-Dimensional Integration 9
1.1 The Ever Increasing Need for Integration 9
1.2 Chip Stacking 10
1.3 Benefits and Challenges of 3D Integration 12
1.3.1 Benefits 12
1.3.1.1 Heterogeneous Integration 12
1.3.1.2 High Degree of Integration in a Small Form Factor 13
1.3.1.3 Improved Power Consumption 13
1.3.1.4 Cost Benefits 14
1.3.2 Technical Challenges 14
1.3.2.1 Process Steps 14
1.3.2.2 Operating Temperature 15
1.3.2.3 Mechanical Stability 15
1.3.2.4 Testing 16
1.3.2.5 Bonding Strategies 16
1.3.3 Business Challenges 17
1.3.3.1 Liability 17
1.3.3.2 Cost Reduction 17
1.3.3.3 Vendor Interfaces 17
1.3.3.4 Standardization 18
1.3.3.5 Design Kits 18
1.4 Purpose of this Book 18
1.5 Book Contents 19
References 20
Chapter 2: TSV-Based 3D Integration 21
2.1 Introduction 21
2.1.1 Initial Studies and Experiments 21
2.1.2 Advanced 3D Packaging 23
2.1.3 Recent Progress in 3D IC Technology 26
2.1.4 3D IC Technology in the ITRS Roadmap 27
2.2 TSV-3D Integration Technologies 28
2.2.1 Introduction 28
2.2.2 TSV Design 28
2.2.3 SOI-Based TSV Technology 31
2.3 TSV Process Integration 32
2.3.1 Stack Alignment 32
2.3.2 Stack Bonding 32
2.3.3 TSV Etching and Filling 33
2.4 Characterization of TSV Processes 34
2.4.1 Physical Characterization 34
2.4.2 Electrical Characterization 34
2.4.3 3D vs. 2D Chip Yield 35
2.5 TSV-Based Chips 35
2.5.1 3D Design Challenges 35
2.5.2 Functional 3D Chips with TSV 36
2.6 Future Challenges 37
References 39
Chapter 3: TSV Characterization and Modeling 41
3.1 Definition and Structure of a TSV 41
3.2 Electrical Characteristics of a TSV: RTSV., CTSV., LTSV 43
3.2.1 TSV Resistance 43
3.2.2 TSV Capacitance 45
3.2.2.1 TSV Capacitance vs. Supply Voltage 48
3.2.2.2 TSV Crosstalk 49
3.2.2.3 TSV Leakage Current and Breakdown Voltage 51
3.2.3 TSV Inductance 51
3.3 Impact of TSV Geometry and Material Parameters on RTSV and CTSV 52
3.4 Electrical Modeling of a TSV 54
3.4.1 Impact of TSV on Interconnect Links 55
3.5 Conclusions 56
References 56
Chapter 4: Homogeneous 3D Integration 58
4.1 Introduction 58
4.2 3D Assembly Options 58
4.2.1 W2W Alignment 59
4.3 3D Bonding Options 60
4.4 Wafer-to-Wafer Assembly 60
4.5 Die-to-Wafer Assembly 63
4.6 Designing a 3D Device 65
4.6.1 Other Design Considerations 66
4.7 TSV Options 66
4.7.1 How Big and How Many? 66
4.7.2 Tungsten or Copper? 67
4.7.3 Other TSV Factors 69
4.8 Tools 71
4.9 Modeling 3D Circuits 71
4.9.1 Thermal Modeling 72
4.9.2 Yield Effects 72
4.10 Testing for 3D 73
4.11 Design-for-Test Meets Repair and Redundancy 74
4.12 A Case Example: Tezzaron 3D DRAM 75
4.12.1 Customization 75
4.12.2 Process Separation 76
4.12.3 Improving Latency 76
4.12.4 Improving Yield 77
4.12.5 Reducing Cost 77
4.12.6 Reducing Power 78
4.13 Summary 78
Chapter 5: 3D Physical Design 79
5.1 Introduction 79
5.2 3D Routing and Thermal TSV Planning 81
5.2.1 Problem Formulation 81
5.2.2 3D Global Routing Algorithms 83
5.2.2.1 Initial 3D Global Routing 85
5.2.2.2 Signal TS Via Planning 85
5.2.2.3 Thermal TS Via Planning 86
5.3 3D Placement 88
5.3.1 Problem Formulation 88
5.3.1.1 Wirelength Objective Function 89
5.3.1.2 Overlap-Free Constraints 89
5.3.1.3 Thermal Awareness 90
5.3.2 Overview of Existing 3D Placement Approaches 91
5.3.3 Modeling of 3D Overlap-Free Constraints 92
5.4 3D Floorplanning 94
5.4.1 Problem Formulation 94
5.4.1.1 3D Floorplanning with 2D Blocks 95
5.4.1.2 3D Floorplanning with 3D Blocks 96
5.4.2 3D Floorplanning Algorithms 97
5.5 3D Floorplanning for 3D Microarchitectural Exploration 99
5.6 Conclusions 104
References 105
Chapter 6: Co-optimization of Power, Thermal, and Signal Interconnect for 3D ICs 108
6.1 Introduction 108
6.2 Overview of 3D Physical Design Flow 109
6.3 Thermofluidic Interconnect for 3D ICs 112
6.3.1 Microfluidic Channel-Based Cooling 112
6.3.2 Thermal Analysis 114
6.3.3 Routing Requirements for Thermofluidic Network 115
6.4 Power Delivery Network for 3D ICs 117
6.4.1 3D Power Distribution Network 117
6.4.2 Noise Analysis 118
6.4.3 TSV RLC Parasitic Modeling 119
6.4.3.1 Inductance Modeling 119
6.4.3.2 Resistance and Capacitance Modeling 120
6.4.4 Routing Requirements for Power Delivery Network 121
6.5 Signal Interconnect for 3D ICs 123
6.5.1 Geometries of Wires and Vias 123
6.5.2 Routing Capacity Calculation 124
6.6 Design of Experiments 125
6.6.1 Overall Design Flow 126
6.6.2 Designing the Experiments 126
6.6.3 Design Optimization 128
6.7 Experimental Results 128
6.7.1 Routability and Congestion Analysis 129
6.7.2 Thermal Analysis 130
6.7.3 Power Noise Analysis 134
6.7.4 Correlations Among Knobs and Metrics 136
6.7.5 Optimization Results and Comparison 137
6.8 Conclusions 140
References 140
Chapter 7: PathFinding and TechTuning 142
7.1 Definition of Requirements for 3D Design Ecosystem 142
7.1.1 2D Design Experiences 142
7.1.2 Incremental Causes for Design Specification Instability in 3D 143
7.1.3 Incremental Causes for Design Enablement Instability in 3D 145
7.1.4 3D Design Ecosystem 146
7.2 PathFinding Design Methodology 148
7.2.1 Introduction to PathFinding 148
7.2.1.1 Motivation 148
7.2.1.2 PathFinding: The Vision 150
7.2.1.3 Requirements for Practical Pathfinding Tool Chain 152
7.2.2 PathFinding: Practical Tool Chain 153
7.2.2.1 3D System Architecture 153
7.2.2.2 RTL Elaboration 154
High-Level Synthesis for Processing Elements 157
High-Level Synthesis for Communication 158
7.2.2.3 3D Design Prototyping 159
7.2.2.4 3D Design Authoring 160
7.2.2.5 Extraction of Estimates 160
7.3 TechTuning 160
7.3.1 TechTuning Objectives 161
7.3.2 TechTuning Implementation 162
7.3.2.1 TechTuning for Mechanical Stress Management 163
7.3.2.2 TechTuning for Thermal Management 169
7.3.3 TechTuning Infrastructure 173
7.3.4 Compact Thermal and Mechanical Modeling 175
7.4 Case Studies 177
7.4.1 High-Level Synthesis for Computation 177
7.4.2 Communication Infrastructure Case Study and PathFinding Feedback Link to the Compact Thermal and Mechanical Models178
7.4.2.1 PathFinding 178
7.4.2.2 TechTuning 182
7.4.3 Packaging Case Study 183
7.5 Summary and Conclusions 188
References 188
Chapter 8: 3D Stacking of DRAM on Logic 191
8.1 Introduction 191
8.1.1 Why Focus on DRAM? 191
8.2 DRAM Structure and Overview 192
8.2.1 Fundamental Structures of Dynamic and Static Memories 193
8.2.2 Fundamentals of DRAM 194
8.2.3 DRAM Internals 195
8.2.4 Hiding DRAM Latency 196
8.2.5 Interconnect Options for SDRAM 197
8.3 The DRAM Bottleneck in Embedded Systems 198
8.3.1 Overview of Current Embedded System Designs 198
8.3.2 Embedded Application Overview 199
8.3.3 Embedded Applications’ System Demands 200
8.4 TSVs as an Enabler for Next-Generation Platforms 201
8.4.1 Current-Generation Platform Introduction 202
8.4.1.1 Intrasystem Interfaces Benefits from TSVs Electric and Geometric Characteristics 202
8.4.1.2 Reducing Off-Chip Communication Requirements 202
8.4.2 A Promising Near-Term DRAM Interface Direction 205
8.4.2.1 DRAM to Logic Interface Redesign 205
8.4.2.2 Three Alternative Scenarios 206
8.4.2.3 Power Considerations 206
8.4.2.4 Application-Specific Results for a Wider Bus Interface 208
8.4.3 Potential Next-Generation DRAM-on-Logic Architectures 210
8.4.3.1 Eight Levels of DRAM with Novel MCs 210
8.4.3.2 Ultra-High Bandwidth Solutions as a Solution for Low-Power ASIC Designs 211
8.4.3.3 Standardization of Interchip TSV Connections 212
8.5 Conclusion 213
References 214
Chapter 9: Microprocessor Design Using 3D Integration Technology 215
9.1 Introduction 215
9.2 The Influence of Various 3D Integration Technology on Microprocessor Design 216
9.3 Designing 3D Processor Architecture 217
9.3.1 Wire Length Reduction 217
9.3.1.1 Latency Improvement 218
9.3.1.2 Power Reduction 219
9.3.2 Memory-Bandwidth Improvement 219
9.3.3 Heterogenous Integration 221
9.3.4 Cost-Effective Microprocessor Design 222
9.3.5 Three-Dimensional NoC Architecture 223
9.4 Case Study 1: Fine-Granularity 3D Microprocessor Design 224
9.4.1 Three-Dimensional Cache Design 225
9.4.2 Instruction Scheduler 228
9.4.3 Three-Dimensional Arithmetic Design 231
9.5 Experimental Results 233
9.6 Challenges for 3D Architecture Design 238
References 238
Chapter 10: 3D Through-Silicon Via Technology Markets and Applications 241
10.1 Drivers for Through-Silicon Via Applications 241
10.2 TSV Applications 241
10.2.1 Image Sensors 241
10.2.2 Memory 242
10.2.3 Processor and Memory 243
10.2.4 Field Programmable Gate Arrays 244
10.3 Remaining Challenges 244
10.3.1 Technical Challenges 244
10.3.2 Sourcing Challenges 245
References 246
Index 247