Time-interleaved Analog-to-Digital Converters (eBook)

Preface 6
Contents 8
About the Author 11
Nomenclature 12
Introduction 14
Analog-to-Digital Conversion 14
Architecture 16
Outline 17
Time-interleaved Track and Holds 18
Introduction 18
Mismatch Between Channels 19
Origin of Spurious Tones 19
Bandwidth Mismatch 22
Performance Improvement by Increasing the Nominal Channel Bandwidth 24
Bandwidth Mismatch Split into Resulting Gain and Phase Mismatch 25
Time-interleaved Track and Hold Architectures 25
Architecture Without a Frontend Sampler 26
Resetting of the Sample Capacitor 28
Input Capacitance 28
Architecture with a Frontend Sampler 30
Input Bandwidth and Settling-time Requirements 32
Increasing the Input Bandwidth 33
Conclusions on Architectures 35
Track and Hold Buffers 35
Even-order Distortion 36
Buffer Distortion 36
Input Capacitance 38
Distortion at High Frequencies with a Capacitive Load 39
Bottom-plate Sampling in a Time-interleaved ADC 41
Number of Channels 42
Sub-ADCs 43
Dependency on Resolution 44
Guidelines 45
Calibration 45
Offset Calibration 47
Gain Calibration 47
Timing Calibration 47
Bandwidth Calibration 48
Jitter Requirement on the Sample-clock 48
Summary and Conclusions 50
Sub-ADC Architectures for Time-interleaved ADCs 52
Introduction 52
The Successive Approximation ADC 53
Standard SA-ADC 53
Architectures to Reduce the DAC Settling Time 54
Conventional SA-ADC Architecture 55
Variable Settling Times 55
SA-ADC with Overranging 57
Single-sided Overrange Technique 59
SA-ADC with Two Comparators in Parallel 60
SA-ADC Architecture Comparison 61
Optimum Number of Conversion Steps 62
Time-constant of a DAC 63
Total Conversion Time as a Function of the Number of Steps 65
Look-ahead Logic 66
Comparator 67
Comparator Accuracy 67
Comparator Offset Requirements 70
Efficiency of SA-ADC Versus Pipeline ADC 70
SA-ADC 72
Minimizing the Load Capacitance to Increase the SNR 74
Neglecting kT/C Noise 74
Signal-to-Noise Ratio 75
Pipeline Converter 76
Amplifier Noise 77
Signal-to-Noise Ratio 79
Comparison and Conclusions on Power Efficiency 80
Summary and Conclusions 81
Implementation of a High-speed Time-interleaved ADC 83
Introduction 83
Clock Generation 84
Clock Buffer 85
Control Circuit for the CML Signal-swing 86
CML Clock-phase Generator 87
CML to CMOS Conversion Circuit 89
Track and Hold 90
Bootstrapping of the Sample-switch 90
Signal Independent Turn-off Delay 92
Reliability 94
Simplified Bootstrap Implementation 95
Implementation 96
Low-skew Switch-driver 97
Clock Generation for the T& H
Buffer 102
Sub-ADC 103
Channel Timing 105
SA-ADC 106
Clock Generation 107
Comparator 109
Digital Control Logic Implementing the Single-sided Overrange Technique and the Look-ahead Functionality 111
DAC of the SA-ADC 115
Decoder 117
DAC of the Sub-ADC 117
Connections Between DAC Ladders 118
Binary to 1-out-of-32 Decoder 118
Interstage Amplifier 120
Re-sampler 123
Calibration 125
Offset Calibration 126
Gain Calibration 126
Layout 128
Measurements 129
Measurement Setup 129
Measurement Results 131
Single Channel Performance 131
All Channel Performance 132
Improved Design 134
Measurement Results of the Improved Design 134
Conclusions 136
Summary and Conclusions 137
Summary 137
Conclusions 139
Original Contributions 140
Recommendations for Future Research 141
Bibliography 142
Index 146