Analog Circuit Design (eBook)

Prof. Arthur van Roermund and Prof. Michiel Steyaert have been editing the best papers from the yearly Advances in Analog Circuit Design workshop into a book for the past 5 years. Dr. Herman Casier is new to the editing trio, he brings excellent input from industry.

Analog Circuit Design 
1 
Preface 
4 
Series on Integrated Circuits and Systems 4
Part I Smart Data Converters 8
1 LMS-Based Digital Assisting for Data Converters 9
1.1 Introduction 9
1.2 High-Resolution ADCs 10
1.3 Limits of ADC Resolution 13
1.4 Zero-Forcing LMS Algorithm 14
1.5 LMS-Based Calibration of the Pipelined ADC 15
1.5.1 Measurement Time and Dither Magnitude Constraints 16
1.5.2 Signal-Dependent Dithering Under Two Constraints 17
1.5.3 Linearity Improvement 19
1.5.4 Opamp Non-linearity Calibration 20
1.6 Noise Leakage Calibration in CT Cascaded Modulator 21
1.6.1 CT-to-DT Transform 22
1.6.2 Calibrated Cascaded Modulator 23
1.7 Conclusions 25
References 26
2 Pipelined ADC Digital Calibration Techniques and Tradeoffs 28
2.1 Introduction 28
2.2 Review of Error Sources in Pipelined ADCs 29
2.2.1 Gain Errors 29
2.2.2 DAC Errors 31
2.3 Digital Calibration Techniques 31
2.3.1 Digital Gain Error Calibration 32
2.3.2 DAC Gain Error Calibration 32
2.3.3 Foreground Calibration Techniques 33
2.3.4 Background Calibration 34
2.4 Rapid Background Calibration Techniques 35
2.4.1 Slow but Accurate Parallel ADC 35
2.4.2 Split-ADC Gain Error Calibration 36
2.4.3 Rapid DAC and Gain Error Correction 37
2.5 Using Digital Calibration to Build Low Power `Smart-ADCs' 41
2.5.1 Open Loop, Non-linear Gain Error Calibration 41
2.5.2 Capacitive Charge Pump Based Pipelined ADC 43
2.6 Summary 46
References 46
3 High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters 48
3.1 Introduction 48
3.2 Digital Calibration of Non-Linearity 50
3.2.1 DAC Non-linearity 51
3.2.2 Stage Gain Non-linearity 52
3.3 Range-Scaling in the First Pipeline Stage 53
3.3.1 Power Consumption in a Noise-Limited ADC 53
3.3.2 Circuit Implementation 54
3.4 SHA-Less Architecture 55
3.5 A 1.2V 14b 100MS/s ADC in 90nm CMOS 56
3.5.1 ADC Architecture 57
3.5.2 Measured Results 58
3.6 Conclusions 63
References 63
4 A Signal Processing View on Time-Interleaved ADCS 65
4.1 Introduction 65
4.2 Time-Interleaved ADCs 66
4.3 Modeling Time-Interleaved ADCs 67
4.4 Digital Calibration of Linear Channel Mismatches 70
4.4.1 Digital Correction Methods 71
4.4.1.1 Time Offset Mismatches 72
4.4.1.2 Frequency Response Mismatches 75
4.4.2 Digital Identification Methods 77
4.4.2.1 Off-line Identification 78
4.4.2.2 On-line Identification 79
4.5 Conclusions 81
References 81
5 DAC Correction and Flexibility, Classification, New Methods and Designs 83
5.1 Introduction 83
5.2 Correction Methods for Current-Steering DACs 84
5.2.1 Classification 84
5.2.2 New Correction Methods Based on Parallel Sub-DACs 87
5.2.2.1 New Method 1: High Level Mapping 87
5.2.2.2 New Method 2: Suppression of Harmonic Distortion 88
5.2.2.3 New Method 3: Self-Calibration of Binary Currents 90
5.3 Analysis of DAC Self-Calibration Methods 91
5.3.1 Self-Measurement Block 91
5.3.2 Algorithm Block 92
5.3.3 Self-Correction Block 94
5.4 Parallel Current-Steering DACs for Flexibility and Smartness 95
5.5 Design Examples and Measurements 97
5.5.1 Unary Currents Self-Calibration in a 12-bit 250nm DAC 97
5.5.2 Both Unary and Binary Currents Self-Calibration in a 12-bit 180nm Quad-Core Flexible DAC 102
5.6 Conclusions 106
References 108
6 Smart CMOS Current-Steering D/A-Converters for Embedded Applications 110
6.1 Introduction 110
6.2 A Multimode -DAC 112
6.3 A 13-b 200MS/s Background-Calibrated DAC 116
6.3.1 Converter Architecture 117
6.3.2 Segment Boundary Calibration 118
6.3.3 Randomization of the Calibration Period 120
6.3.4 Low-Bandwidth High-Resolution Mode 121
6.4 A 13-b 50MHz Bandwidth DAC with Active Output Stage 123
6.4.1 Converter Architecture 124
6.4.2 Direct Segment Calibration 124
6.5 Conclusions 128
References 128
Part II Filters On-Chip 130
7 Synthesis of Low-Sensitivity Analog Filters 131
7.1 Introduction 131
7.2 Passive Filters 132
7.2.1 Doubly Resistively Terminated Lossless Networks 132
7.2.2 Reflection Function 133
7.2.3 Sensitivity 134
7.2.4 Passband Sensitivity 134
7.3 Errors in the Elements in Doubly Terminated Filters 138
7.3.1 Errors in the Terminating Resistors 140
7.3.2 Effects of Lossy Elements 141
7.4 LC Filters with Diminishing Ripple 142
7.5 Approximations with Small Group Delay 143
7.6 Design of Doubly Terminated LC Filters 146
7.7 Conclusions 147
References 147
8 High-Performance Continuous-Time Filters with On-Chip Tuning 148
8.1 Introduction 148
8.2 Linear Operational Transconductance Amplifiers (OTAs) 149
8.2.1 Advanced Linearization Techniques 150
8.2.2 OTA Linearization Using Non-linear Elements 151
8.2.3 Design Example: A 30-MHz Elliptic Filter 154
8.3 Broadband Tuning for Interference Suppression in UWB Receivers 155
8.3.1 Analog LMS Control for Maximizing Attenuation 158
8.3.2 Interference Detection and Center Frequency Tuning 160
8.3.3 Experimental Results 161
8.4 Calibration of the Noise Transfer Function in a BP Modulator 162
8.5 Conclusion 165
References 166
9 Source-Follower-Based Continuous Time Analog Filters 168
9.1 Introduction 168
9.2 Source-Follower Circuit 170
9.3 A Source-Follower-Based Cascade CT Filter 172
9.3.1 Linearity Performance 174
9.3.2 Noise Performance 175
9.3.3 DC-Gain Loss 175
9.3.4 Minimum Supply Voltage 176
9.3.5 Silicon Prototype Experimental Results: A Fourth-Order Cascade SFB CT Filter for WLAN Receivers 176
9.4 A Source-Follower-Based Ladder CT Filter 180
9.4.1 Filter Circuital Topology 182
9.4.2 Minimum Supply Voltage 182
9.4.3 Silicon Prototype Experimental Results: A Sixth-Order Ladder SFB CT Filter for UWB Receivers 182
9.5 Conclusions 186
References 187
10 Reconfigurable Active-RC Filters with High Linearity and Low Noise for Home Networking Applications 189
10.1 Introduction 189
10.2 Architecture Selection 190
10.3 Architectural-Level Design Considerations 192
10.3.1 Optimized for Noise 192
10.3.2 Optimized for Speed 192
10.3.3 Optimized for Linearity 193
10.4 Circuit-Level Design Considerations 193
10.4.1 Reconfigurable Filter and Gain Stages 194
10.4.2 PGA Opamps with Adaptive Compensation 195
10.4.3 Tuning Loops 196
10.5 Experimental Results 197
10.6 Conclusions 201
References 201
11 On-Chip Instantaneously Companding Filters for Wireless Communications 203
11.1 Introduction 203
11.2 Companding Switched Capacitor Filter Implementation 205
11.3 Opamp's DC Offset Cancellation 211
11.4 WLAN Receiver Baseband Signal Chain 214
11.5 Simulation Results 215
11.6 Summary 217
References 218
12 BAW-IC CO-Integration Tunable Filters at GHz Frequencies 219
12.1 Introduction 219
12.2 BAW Technology 220
12.2.1 BAW Resonators 220
12.2.2 Electromechanical and Electrical Model of a BAW Resonator 221
12.3 BAW Resonator Filters 222
12.3.1 BAW Ladder Filters 223
12.3.2 BAW Lattice Filters 223
12.3.3 BAW Filters Synthesis Method 225
12.4 Tunable BAW Resonators 226
12.5 Design of an Electronically Tunable BAW Filter for Zero IF W-CDMA Receivers 228
12.5.1 BAW Tuning Cell Implementation 229
12.5.2 BAW Filter Implementation 231
12.5.3 BAW Filter Measurement Results 233
12.6 Tuning Circuitry for BAW Filters 234
12.6.1 Preliminary Discussion 234
12.6.2 Indirect Tuning Method I: PLL with a VCO as Master Cell 236
12.6.3 Indirect Tuning Method II: FLL with Envelope Detection 237
12.7 Design of a Digital Tuning Circuitry for a BAW Tunable Filter 238
12.7.1 Circuit Implementation 239
12.7.2 Measurement Results 240
12.8 Conclusions and Perspectives 242
References 243
Part III Multi-mode Transmitters 245
13 Multimode Transmitters: Easier with Strong Nonlinearity 247
13.1 Introduction 247
13.2 Architecture 248
13.3 Design Issues 249
13.4 Performance Measurements 253
13.5 Conclusions 256
References 257
14 RBS High Efficiency Power Amplifier Research – Challenges and Possibilities 258
14.1 Introduction 258
14.2 Power Amplifier Efficiency in an RBS Transmitter Context 259
14.3 Software Defined Radio (SDR) RBS 260
14.3.1 SDR RBS 260
14.4 Wide RF Bandwidth Power Amplifier Design 261
14.5 Efficiency Enhancement Techniques 263
14.5.1 Envelope Tracking Transmitter Architecture 265
14.5.2 Third Order Doherty 266
14.5.3 Pulsed Transmitter Architectures 267
14.5.3.1 Three Examples of Pulsed Transmitter Architectures 269
Baseband or Envelope PM 269
Cartesian PM 269
RF PM 270
14.5.3.2 Efficient Filtering of the Residual Quantization Distortion 271
14.6 Conclusions 271
References 272
15 Multi-Mode Transmitters in CMOS 273
15.1 Introduction 273
15.2 Direct Quadrature Voltage Modulator for Cellular Applications 274
15.2.1 Direct Quadrature Voltage Modulator 275
15.2.2 25% Duty-Cycle LO Generation 277
15.2.3 Measurement Results 278
15.3 Digital Polar Transmitter for Connectivity Applications 281
15.3.1 Direct Digital Polar Transmitter 284
15.3.2 Multi-phase Clocking 285
15.3.3 IC Implementation 286
15.3.4 Measurement Results 289
15.4 Conclusions 291
References 291
16 Challenges for Mobile Terminal CMOS Power Amplifiers 293
16.1 Introduction 293
16.2 Efficiency Improvement Techniques 294
16.3 Changing the RF Path 294
16.3.1 Discrete Class B 296
16.3.2 Power Combining 296
16.4 Changing the BB Path 298
16.4.1 Digital Polar 300
16.5 Conclusions 301
References 301
17 Multimode Transmitters with -Based All-Digital RF Signal Generation 303
17.1 Introduction 303
17.2 Modulation for All-Digital RF Signal Generation 305
17.2.1 What Can Modulation Bring in Integrated Transmitters? 305
17.2.2 IF DAC 306
17.2.3 1-bit RF DAC 306
17.2.4 Multi-bit RF DAC 307
17.3 Switched Power Amplification 308
17.3.1 Current and Voltage-Mode Switched Power Amplifier 308
17.3.2 Power Combining 309
17.4 Discussion on Digital and Mixed-Signal Blocks Implementation 311
17.4.1 Oversampling Up to RF Frequencies 311
17.4.2 Sampling Clock Synchronization on RF LO 311
17.4.3 Implementing the Modulator 312
17.4.3.1 Pipelined MASH Structures 312
17.4.3.2 High-Speed Modulator Implementation Using Redundant Representation 313
17.4.3.3 Going Further: Adaptive Placement of Complex Poles and Zeros of the NTF 314
17.4.4 Mixer and Digital-to-Analog Conversion 315
17.5 Dealing with Quantization Noise 316
17.5.1 BAW Filtering 316
17.5.2 RF Semi-Digital FIR Filtering 317
17.6 Conclusion 319
References 320
18 Switched Mode Transmitter Architectures 322
18.1 Introduction 322
18.2 Power Amplifiers 325
18.3 Envelope Modulation Techniques 327
18.4 Polar Switched Mode Architectures 329
18.5 Cartesian Switched Mode Architectures 333
18.6 RF Pulse Width Modulators 334
18.7 Delta-Sigma RF Pulse Width Modulation 335
18.8 Conclusions 338
References 338