Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters (eBook)

Dr. Sin is currently the Secretary of IEEE Solid-State Circuit Society (SSCS) Macau Chapter, and Treasurer/Secretary of IEEE Macau CAS/COM Joint Chapter and the Member of Executive Committee – Academic Affair of IEEE Macau, and has been the member of Technical Program and Organization Committee of the 2004 IEEJ AVLSI Workshop, Technical Session Chair of 2006 RIUPEEEC Conference, as well as the Special Session Co-Chair and Technical Program Committee Member of 2008 IEEE APCCAS Conference, Referee of IEEE Transaction of Instrumentation and Measurement and IEEE ISCAS Conference. He received the Chipidea Microelectronics Prize – Postgraduate Level in 2008 for outstanding Academic and Research achievements in Microelectronics, as well as the Financial Support Award for Student Paper Contest in 2005 International Symposium on Circuits and Systems (ISCAS) held in Kobe, Japan, the Paper with Certificate of Merit for the 2006 RIUPEEEC Conference, as well as Award of Dean Honor List, Faculty of Science and Technology, University of Macau, in 1999-2000 and 2000-2001 respectively. Dr. U is currently Senior Member of IEEE, the Industrial Relationship Officer of IEEE Macau Section and the Chairman of IEEE Macau CAS/COMM and SSC chapters. He has been with technical review committee of various IEEE journals and conferences. He was the chairman of the local organization committee of IEEJ AVLSIWS'04, Technical Program co-Chair of IEEE APCCAS'08. He is also the Program Co-chair of ICICS'09 and Technical Program Committee of ASSCC. Prof. Rui Martins is an IEEE Fellow, was the Founding Chairman of the IEEE Macau Section from 2003 to 2005, and of the IEEE Macau Joint-Chapter on Circuits And Systems (CAS) / Communications (COM) from 2005 to 2008 [World Chapter of the Year 2009 of the IEEE Circuits And Systems Society (CASS)]. He was the General Chair of the 2008 IEEE Asia-Pacific Conference on Circuits And Systems – APCCAS’2008, and was elected Vice-President for the Region 10 (Asia, Australia, the Pacific) of the IEEE Circuits And Systems Society (CASS), for the period of 2009 to 2010. He is Associate Editor of the IEEE Transactions on Circuits and Systems II – Express Briefs,for the period of 2010 to 2011. He was the recipient of 2 government decorations: the Medal of Professional Merit from Macao Government (Portuguese Administration) in 1999, and the Honorary Title of Value from Macao SAR Government (Chinese Administration) in 2001.

Preface 8
Acknowledgement 10
Contents 12
Abbreviations 16
Chapter 1: Introduction 18
1.1 Low-Voltage High-Speed Analog-to-Digital Conversion 18
1.2 Applications of High-Speed ADCs 20
1.3 Deep-Submicron CMOS ADCs Designs 22
1.4 Main Objective and Design Challenges 24
References 25
Chapter 2: Challenges in Low-Voltage Circuit Designs 28
2.1 Introduction 28
2.2 The Impact of CMOS Technology Scaling 28
2.3 Design Challenges: Intrinsic Performance Degradation 30
2.3.1 Transconductance Degradation 30
2.3.2 Output Resistance Degradation 31
2.3.3 Trends of Unity-Gain Frequency in Technology Scaling 32
2.4 Circuit Level Design Challenges: Opamps 32
2.5 Circuit Level Design Challenges: Switches 34
2.5.1 Switch Positioning 36
2.5.2 Clock Boosting 36
2.5.3 Bootstrapped Switches 37
2.5.4 Switched-Opamp 38
2.5.5 Reset-Opamp 39
2.5.6 Switched-RC Techniques 40
2.6 Summary 41
References 42
Chapter 3: Advanced Low Voltage Circuit Techniques 44
3.1 Introduction 44
3.2 Virtual-Ground Common-Mode Feedback and Output Common-Mode Error Correction 45
3.2.1 Low-Voltage CMFB Design Challenges 45
3.2.2 Novel Virtual Ground CMFB Technique 46
3.2.3 Practical Implementation of VG-CMFB 48
3.2.4 Output Common-Mode Error Correction 49
3.3 Cross-Coupled Passive Sampling Interface 50
3.3.1 Problems in Existing Solutions 50
3.3.2 Cross-Coupled Passive Sampling Interface 52
3.4 Voltage-Controlled Level Shifting 56
3.5 Feedback Current Biasing Technique 57
3.6 Low-Voltage Finite-Gain-Compensation 60
3.6.1 The Need for Finite-Gain Compensation 60
3.6.2 Auxiliary Differential-Difference Amplifier 64
3.7 Low-Voltage Offset-Compensation 66
3.7.1 The Crossed-Coupled S/H 66
3.7.2 The SC Amplifier 68
3.8 Summary 69
References 70
Chapter 4: Time-Interleaving: Multiplying the Speed of the ADC 72
4.1 Introduction 72
4.2 Time-Interleaved ADC Architecture 72
4.3 Channel Mismatch Analysis 74
4.4 Offset Mismatch 78
4.5 Gain Mismatch 80
4.6 Timing Mismatch 83
4.7 Bandwidth Mismatch 85
4.8 Summary 89
References 90
Chapter 5: Design of a 1.2 V, 10-bit, 60-360 MHz Time-Interleaved Pipelined ADC 92
5.1 Introduction 92
5.2 The Overall ADC Architecture 93
5.3 Prototype Circuit-Level Design 94
5.3.1 Resistively Demultiplexed Front-End Sample-and-Hold 94
5.3.2 1.5 b/Stage Multiplying-Digital-to-Analog-Converter (MDAC) 95
5.3.3 Current-Mode Sub-ADC Design 97
5.3.4 Programmable Timing-Skew Insensitive Clock Generator 98
5.3.5 Noise Analysis 99
5.3.6 Channel Mismatch Analysis 102
5.4 Layout Considerations 103
5.5 Simulation Results 105
5.5.1 Opamp Simulations 105
5.5.2 Front-End S/H 105
5.5.3 Current-Mode Comparator 107
5.5.4 The Overall ADC Simulations 109
5.6 Summary 111
References 111
Chapter 6: Experimental Results 113
6.1 Introduction 113
6.2 The Prototype PCB Design 113
6.2.1 The Floor Plan 113
6.2.2 Power Supply Considerations 114
6.2.3 Signal Trace Routing 116
6.3 Measurement Setup and Results 116
6.3.1 Time-Domain Digital Output Code Pattern 118
6.3.2 Static Performance 118
6.3.3 Dynamic Performance 120
6.4 Summary 124
References 127
Chapter 7: Conclusions and Prospective for Future Work 129
7.1 Conclusions 129
7.2 Prospective for Future Work 130
7.2.1 Low-Noise and Low-Voltage Circuit Techniques Implementation 131
7.2.2 Fully Dynamic ADC Implementations 131
7.2.3 SC Circuits Implemented with Open-Loop Amplifiers 131
7.2.4 Digital Calibration 132
References 132
Appendix A Operating Principle of VG-CMFB with O-CMEC 133
Appendix B Mathematical Analysis of Bandwidth Mismatches 136
Appendix C Noise Analysis of Advanced Reset-Opamp Circuits 140
Appendix D Special Case in Gain Mismatch 145
Index 146