Dependability in Electronic Systems (eBook)

Preface 5
Reference 6
Acknowledgements 7
Contents 9
List of Figures 13
List of Tables 21
List of Acronyms 22
1 Introduction 25
1.1 Trends in Failure Cause and Countermeasure 25
1.2 Contents and Organization of This Book 27
1.3 For the Best Result 29
References 29
2 Terrestrial Neutron-Induced Failures in Semiconductor Devices and Relevant Systems and Their Mitigation Techniques 31
2.1 Introduction 31
2.1.1 SER in Memory Devices 31
2.1.2 MCU in Memory Devices 32
2.1.3 SET and MNU in Logic Devices 32
2.1.4 Chip/System-Level SER Problem: SER Estimation and Mitigation 33
2.1.5 Scope of This Chapter 33
2.2 Basic Knowledge on Terrestrial Neutron-Induced Soft-Error in MOSFET Devices 34
2.2.1 Cosmic Rays from the Outer Space 34
2.2.2 Nuclear Spallation Reaction and Charge Collection in CMOSFET Device 35
2.3 Experimental Techniques to Quantify Soft-Error Rate (SER) and Their Standardization 36
2.3.1 The System to Quantify SER -- SECIS 36
2.3.2 Basic Method in JESD89A 37
2.3.2.1 Spallation Neutron Methods 37
2.3.2.2 (Quasi-)Mono-Energetic Neutron Test 37
2.3.3 SEE Classification Techniques in Time Domain 39
2.3.4 MCU Classification Techniques in Topological Space Domain 40
2.4 Evolution of Multi-node Upset Problem 41
2.4.1 MCU Characterization by Accelerator-Based Experiments 41
2.4.1.1 DUTs and Neutron Beams 41
2.4.1.2 MCU Patterns 42
2.4.1.3 Influence of Tap Locations 43
2.4.1.4 MCU Category 44
2.4.1.5 MCU Code 44
2.4.2 Multi-coupled Bipolar Interaction (MCBI) 45
2.5 Simulation Techniques for Neutron-Induced Soft Error 47
2.5.1 Overall Microscopic Soft-Error Model 47
2.5.2 Nuclear Spallation Reaction Models 48
2.5.3 Charge Deposition Model 48
2.5.4 SRAM Device Model 50
2.5.5 Cell Matrix Model 51
2.5.6 Recycle Simulation Method 52
2.5.7 Validation of SRAM Model 53
2.6 Prediction for Scaling Effects Down to 22nm Design Rule in SRAMs 53
2.6.1 Roadmap Assumption 53
2.6.2 Results and Discussions 54
2.6.2.1 Overall Trends 54
2.6.2.2 Charge Deposition Density for Secondary Ions 58
2.6.2.3 Total Charge Collected to Storage Node 59
2.6.2.4 Failed Bit Map (FBM) 60
2.6.2.5 Energy Dependency of SEU/MCU Cross-Section 60
2.6.2.6 Trends in MCU Ratio 62
2.6.2.7 Trends in MCU Multiplicity Distribution 62
2.6.3 Validity of Simulated Results 63
2.7 SER Estimation in Devices/Components/System 64
2.7.1 Standards for SER Measurement for Memories 64
2.7.2 Revisions Needed for the Standards 64
2.7.3 Quantification of SER in Logic Devices and Related Issues 66
2.8 An Example of Chip/Board-Level SER Measurement and Architectural Mitigation Techniques 67
2.8.1 SER Test Procedures for Network Components 67
2.8.1.1 Full and Partial Board Irradiation Test 67
2.8.1.2 Neutron Facility 68
2.8.1.3 Architecture of Test Component 69
2.8.1.4 Test Procedures 71
2.8.2 Results and Discussions 73
2.8.2.1 Test Results 73
2.8.2.2 Efficacy of Partial Board Irradiation Test 73
2.8.2.3 Correlation Between the Irradiation Test and Field Data 74
2.9 Hierarchical Mitigation Strategies 75
2.9.1 Basic Three Approaches 75
2.9.2 Design on the Upper Bound (DOUB) 76
2.10 Inter Layer Built-In Reliability (LABIR) 80
2.11 Summary 81
References 83
3 Electromagnetic Compatibility 88
3.1 Introduction 88
3.2 Quantitative Estimation of the EMI Radiation Based on the Measured Near-Field Magnetic Distribution 91
3.2.1 Measurement of the Magnetic Field Distribution Near the Circuit Board 91
3.2.2 Calculation of the Electric Current Distribution on the Circuit Board 91
3.2.3 Calculation of the Far-Field Radiated EMI 93
3.3 Development of a Non-contact Current Distribution Measurement Technique for LSI Packaging on PCBs 94
3.3.1 Electric Current Distribution Detection 94
3.3.1.1 Target Specification 94
3.3.1.2 Conventional and Proposed Technique for Obtaining Current Distribution 94
3.3.1.3 High-Resolution Current Detecting Technique 97
3.3.2 The Current Detection Result and Its Verification 97
3.4 Reduction Technique of Radiated Emission from Chassis with PCB 98
3.4.1 Far-Field Measurement of Chassis with PCB 98
3.4.2 Measurements of Junction Current 102
3.4.3 PSPICE Modeling 103
3.4.4 Experimental Validation 108
3.5 Chapter Summary 109
References 111
4 Power Integrity 113
4.1 Introduction 113
4.2 Detrimental Effect and Technical Trends of Power Integrity Design of Electronic Systems and Devices 114
4.2.1 Detrimental Effect by Power Supply Noise on Semiconducting Devices 114
4.2.1.1 Noise Margin Degradation 114
4.2.1.2 On-Chip Clock Timing 115
4.2.1.3 Signal Timing Uncertainty 116
4.2.1.4 Jitter in Single-Ended Signaling 116
4.2.1.5 Jitter in Differential Signaling 118
4.2.2 Trends of Power Supply Voltage and Power Supply Current for CMOS Semiconducting Devices 120
4.2.3 Trend of Power Distribution Network Design for Electronic Systems 122
4.3 Design Methodology of Power Integrity 124
4.3.1 Definition of Power Supply Noise in Electric System 124
4.3.2 Time-Domain and Frequency-Domain Design Methodology 126
4.3.2.1 Time-Domain (TD) Analysis 127
4.3.2.2 Frequency-Domain Analysis 128
4.3.2.3 Target Impedance 129
4.3.2.4 Comparison Between TD and FD Analyses 136
4.4 Modeling and Design Methodologies of PDS 137
4.4.1 Modeling of Electrical Circuit Parameters 138
4.4.1.1 Voltage Regulator Module (VRM) 138
4.4.1.2 Bypass Capacitor 140
4.4.1.3 Land of Bypass Capacitor 141
4.4.1.4 Power and Ground Planes 142
4.4.1.5 VIA 142
4.4.1.6 BGA 142
4.4.1.7 On-Chip Bypass Capacitors 143
4.4.2 Design Strategies of PDS 143
4.4.2.1 Usage of Different Capacitors 145
4.4.2.2 Usage of a Capacitor with Large BQF 145
4.4.2.3 Usage of a Large ESR 146
4.4.2.4 Usage of Multiple Terminal Components 146
4.4.2.5 Place Components as Close as Possible 147
4.5 Simultaneous Switching Noise (SSN) 147
4.5.1 Principle of SSN 148
4.5.2 S--G loop SSN 149
4.5.3 P--G loop SSN 151
4.6 Measurement of Power Distribution System Performance 153
4.6.1 On-Chip Voltage Waveform Measurement 153
4.6.1.1 DAC 153
4.6.1.2 Ring Oscillator 154
4.6.1.3 Delay Observation 157
4.6.2 On-Chip Power Supply Impedance Measurement 159
4.6.2.1 Integrated Power Supply Frequency Domain Impedance Meter (IFDIM) 159
4.6.2.2 Impulse Response Method 160
4.7 Summary 162
References 163
5 Fault-Tolerant System Technology 165
5.1 Introduction 165
5.2 Metrics for Dependability 166
5.2.1 Reliability 166
5.2.2 Availability 167
5.2.3 Safety 169
5.3 Reliability Paradox 170
5.4 Survey on Fault-Tolerant Systems 172
5.5 Technical Issues 175
5.5.1 High Performance 176
5.5.2 Transparency 178
5.5.3 Physical Transparency 178
5.5.4 Fault Tolerance of Fault Tolerance for Ultimate Safety 179
5.5.5 Reliability of Software 182
5.6 Industrial Approach 183
5.6.1 Autonomous Decentralized Systems 185
5.6.2 Space Application 186
5.6.3 Commercial Fault-Tolerant Systems 186
5.6.4 Ultra-Safe System 187
5.7 Availability Improvement vs. Coverage Improvement 188
5.8 Trade-Off Between Availability and Coverage Stepwise Negotiating Voting 188
5.8.1 Basic Concept 188
5.8.2 Hiten Onboard Computer 191
5.8.3 Fault-Tolerance Experiments 192
5.8.3.1 Fault-Injection Experiments 192
5.8.3.2 Field Data 193
5.8.4 Extension of SNV -- Redundancy Management 195
5.9 Coverage Improvement 197
5.9.1 Self-Checking Comparator 198
5.9.2 Optimal Time Diversity 201
5.10 On-Chip Redundancy 206
5.11 High Performance (Commercial Fault-Tolerant Computer) 210
5.11.1 Basic Concepts of TPR Architecture 210
5.11.1.1 System Reconfiguration by Collaboration of Hardware and Software 210
5.11.1.2 Intra-board Fault-Masking 211
5.11.2 System Configuration 211
5.11.3 System Reconfiguration on Fault Occurrence 213
5.11.4 Processing Take-Over on Fault Occurrence 213
5.11.5 Fault Tolerance of Fault Tolerance 214
5.11.5.1 Fault Tolerance of System Reconfiguration 214
5.11.5.2 Fault Tolerance of MPU Checker 214
5.11.6 Commercial Product Model 217
5.12 Current Application Field: X-by-Wire 218
References 220
6 Challenges in the Future 223
References 224
Index 225