On and Off-Chip Crosstalk Avoidance in VLSI Design (eBook)

Preface 5
Acknowledgements 7
Contents 8
List of Figures 14
Part I On-Chip Crosstalk and Avoidance 21
Introduction of On-Chip Crosstalk Avoidance 22
Challenges in Deep Submicron Processes 22
Overview of On-Chip Crosstalk Avoidance 23
Bus Encoding for Crosstalk Avoidance 28
Part I Organization 29
Preliminaries to On-Chip Crosstalk 31
Modeling of On-Chip Interconnects 31
Crosstalk Based Bus Classification 40
Bus Encoding for Crosstalk Avoidance 42
Notation and Terminology 43
Memoryless Crosstalk Avoidance Codes 45
3C-Free CACs 45
Forbidden Pattern Free CAC 46
Code Design 46
Code Cardinality 48
Forbidden Transition Free CAC 50
Code Design 51
Code Cardinality 52
Circuit Implementation and Simulation Results 53
2C-Free CACs 55
Code Construction 56
Code Cardinality and Area Overhead 58
2C Experiments 60
1C-Free Busses 60
Bus Configurations 61
Experimental Results 61
Summary 62
CODEC Designs for Memoryless Crosstalk Avoidance Codes 64
Bus Partitioning Based CODEC Design Techniques 64
Group Complement 65
Proof of Correctness 67
Bit Overlapping 68
FPF-CAC CODEC Design 68
Fibonacci-Based Binary Numeral System 69
Near-Optimal CODEC 70
Optimal CODEC 74
Implementation and Experimental Results 76
FTF-CAC CODEC Design 82
Mapping Scheme 82
Coding Algorithm 83
Implementation and Experimental Results 84
Summary 87
Memory-based Crosstalk Avoidance Codes 90
A 4C-Free CAC 90
A 4C-free Encoding Technique 90
An Example 91
Codeword Generation by Pruning 92
Codeword Generation Using ROBDD 97
Efficient Construction of GkC - freem 97
An Example 99
Finding the Effective kC Free Bus Width from GkC - freem 100
Experimental Results 101
Summary 102
Multi-Valued Logic Crosstalk Avoidance Codes 104
Bus Classification in Multi-Valued Busses 105
Low Power and Crosstalk Avoiding Codingon a Ternary Bus 107
Direct Binary-Ternary Mapping 107
4X Ternary Code 108
3X Ternary Code 110
Circuit Implementations 111
Experimental Results 112
Summary 115
Summary of On-Chip Crosstalk Avoidance 117
Part II Off-Chip Crosstalk and Avoidance 120
Introduction to Off-Chip Crosstalk 121
The Role of IC Packaging 121
Noise Sources in Packaging 123
Inductive Supply Bounce 123
Inductive Signal Coupling 125
Capacitive Bandwidth Limiting 127
Capacitive Signal Coupling 128
Impedance Discontinuities 129
Performance Modeling and Proposed Techniques 131
Performance Modeling 131
Optimal Bus Sizing 131
Bus Encoding 132
Impedance Compensation 133
Advantages Over Prior Techniques 134
Performance Modeling 134
Optimal Bus Sizing 135
Bus Encoding 136
Impedance Compensation 137
Broader Impact of This Monograph 137
Organization of Part II of this Monograph 138
Package Construction and Electrical Modeling 139
Level 1 Interconnect 139
Wire Bonding 139
Flip-Chip Bumping 141
Level 2 Interconnect 143
Lead Frame 143
Array Pattern 144
Modern Packages 145
Quad Flat Pack with Wire Bonding 146
Ball Grid Array with Wire Bonding 147
Ball Grid Array with Flip-Chip Bumping 148
Electrical Modeling 149
Quad Flat Pack with Wire Bonding 149
Ball Grid Array with Wire Bonding 149
Ball Grid Array with Flip-Chip Bumping 150
Preliminaries and TerminologyThis chapter describes the terminology and notation used throughout the rest of this monograph. 151
Bus Construction 151
Logic Values and Transitions 153
Signal Coupling 154
Mutual Inductive Signal Coupling 154
Mutual Capacitive Signal Coupling 155
Return Current 155
Noise Limits 156
Analytical Model for Off-ChipBus Performance 159
Package Performance Metrics 159
Converting Performance to Risetime 160
Converting Bus Performance to didt and dvdt 161
Translating Noise Limits to Performance 162
Inductive Supply Bounce 162
Capacitive Bandwidth Limiting 164
Signal Coupling 165
Impedance Discontinuities 166
Experimental Results 166
Test Circuit 167
Quad Flat Pack with Wire Bonding Results 168
Ball Grid Array with Wire Bonding Results 170
Ball Grid Array with Flip-Chip Bumping Results 171
Discussion 173
Optimal Bus Sizing 175
Package Cost 175
Bandwidth Per Cost 177
Results for Quad Flat Pack with Wire Bonding 177
Results for Ball Grid Array with Wire Bonding 178
Results for Ball Grid Array with Flip-Chip Bumping 178
Bus Sizing Example 180
Bus Expansion Encoder 181
Constraint Equations 181
Supply Bounce Constraints 182
Signal Coupling Constraints 182
Glitch Magnitude Constraints 182
Risetime Degradation Constraints 183
Falltime Degradation Constraints 183
Capacitive Bandwidth Limiting Constraints 184
Impedance Discontinuity Constraints 185
Number of Constraint Equations 186
Number of Constraint Evaluations 186
Encoder Construction 187
Encoder Algorithm 187
Encoder Overhead 189
Decoder Construction 189
Experimental Results 189
3-Bit Fixed didt Example 190
3-Bit Varying didt Example 194
Functional Implementation 196
Physical Implementation 197
TSMC 0.13mm ASIC Process 197
Xilinx 0.35mm FPGA Process 198
Measurement Results 199
Bus Stuttering Encoder 202
Encoder Construction 202
Encoder Algorithm 203
Encoder Overhead 204
Decoder Construction 205
Experimental Results 205
Functional Implementation 207
Physical Implementation 209
TSMC 0.13 '155m ASIC Process 209
Xilinx 0.35'155m FPGA Process 210
Measurement Results 210
Discussion 211
Impedance Compensation 213
Static Compensator 214
Methodology 214
Compensator Proximity 215
On-Chip Capacitors 215
On-Package Capacitors 217
Static Compensator Design 217
Experimental Results 219
Dynamic Compensator 222
Methodology 222
Dynamic Compensator Design 222
Capacitor Design 222
Pass Gate Design 224
Experimental Results 225
Dynamic Compensator Calibration 228
Future Trends and Applications 231
The Move from ASICs to FPGAs 231
IP Cores 234
Power Minimization 235
Connectors and Backplanes 236
Internet Fabric 237
Summary of Off-Chip Crosstalk Avoidance 239
Index 249