VLSI Design for Video Coding (eBook)
XI, 176 Seiten
Springer US (Verlag)
978-1-4419-0959-6 (ISBN)
High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.
This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.
High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.
Preface 5
Contents 7
1 Introduction to Video Coding and H.264/AVC 10
1.1 Introduction 10
1.1.1 Basic Coding Unit 11
1.1.2 Video Encoding Flow 11
1.1.3 Color Space Conversion 11
1.1.4 Prediction of a Macroblock 12
1.1.5 Intraframe Prediction 13
1.1.6 Interframe Prediction 13
1.1.7 Motion Vector 13
1.1.8 Prediction Error 13
1.1.9 Space-Domain to Frequency-Domain Transformation of Residual Error 14
1.1.10 Coefficient Quantization 14
1.1.11 Reconstruction 14
1.1.12 Motion Compensation 14
1.1.13 Deblocking Filtering 15
1.2 Book Organization 15
2 Intra Prediction 19
2.1 Introduction 19
2.1.1 Algorithm 20
2.1.2 Design Consideration 24
2.2 Related Works 27
2.2.1 Prediction Time Reduction Approaches 27
2.2.2 Hardware Area Reduction Approaches 27
2.3 A VLSI Design for Intra Prediction 28
2.3.1 Subtasks Scheduling 28
2.3.2 Architecture 32
2.3.2.1 RL Engine 33
2.3.2.2 Non-RL Engine 33
2.3.3 Evaluation 38
2.4 Summary 38
3 Integer Motion Estimation 39
3.1 Introduction 39
3.1.1 Algorithms 41
3.1.2 Design Considerations 44
3.2 Related Works 45
3.2.1 Architecture 45
3.2.2 Data-Reuse Schemes 51
3.3 A VLSI Design for Integer Motion Estimation 52
3.3.1 Proposed Data-Reuse Scheme 53
3.3.2 Architecture 55
3.3.3 Data Flow 57
3.3.4 Evaluation 60
3.4 Summary 61
4 Fractional Motion Estimation 64
4.1 Introduction 64
4.1.1 Algorithms 65
4.1.2 Design Considerations 68
4.2 Related Works 68
4.3 A VLSI Design for Fractional Motion Estimation 70
4.3.1 Proposed Architecture 70
4.3.2 Proposed Resource Sharing Methodfor SATD Generator 75
4.3.2.1 Analysis of SATD Generator Usage 75
4.3.2.2 Customized Arbitration Scheme 76
4.3.3 Evaluation 79
4.4 Summary 79
5 Motion Compensation 80
5.1 Introduction 80
5.1.1 Algorithms 80
5.1.2 Design Considerations 82
5.2 Related Works 82
5.2.1 Memory Traffic Reduction 83
5.2.2 Interpolation Engine 83
5.3 A VLSI Design for Motion Compensation 84
5.3.1 Motion Vector Generator 84
5.3.2 Interpolator 86
5.3.2.1 Interpolation Engine 87
5.3.2.2 Area-Efficient Chroma Filter 88
5.3.2.3 Fully Utilized Weighted Prediction Engine 88
5.3.3 Evaluation 90
5.4 Summary 90
6 Transform Coding 91
6.1 Introduction 91
6.1.1 Algorithms 91
6.1.1.1 Transform 95
6.1.1.2 Quantization 96
6.1.1.3 Inverse Quantization 97
6.1.1.4 Inverse Transform 98
6.1.1.5 Run Level Coding 99
6.1.1.6 Encoding Process of the Transform Coding Unit 100
6.1.2 Design Consideration 103
6.2 Related Works 103
6.2.1 Multitransform Engine Approaches 103
6.2.2 Trans/Quan or InvQuan/InvTrans Integration Approaches 103
6.3 A VLSI Design for Transform Coding 104
6.3.1 Subtasks Scheduling 104
6.3.2 Architecture 104
6.3.2.1 Multitransform Engine 105
6.3.2.2 Combined Q/IQ Engine 106
6.3.2.3 RLC Engine 107
6.3.2.4 Organization of the Coefficient Memory 108
6.3.3 Evaluation 112
6.4 Summary 112
7 Deblocking Filter 113
7.1 Introduction 113
7.1.1 Deblocking Filter Algorithm 114
7.1.1.1 Filtering Order 114
7.1.1.2 Boundary Strength, Thresholds, and FilterSampleflag 115
7.1.1.3 Edge Filter 118
7.1.2 Subtasks Processing Order 118
7.1.3 Design Considerations 119
7.1.3.1 Processing Cycles 120
7.1.3.2 External Memory Traffic 120
7.1.3.3 Working Frequency 120
7.1.3.4 Hardware Cost 120
7.1.3.5 Skip Mode Support for Eliminating Unnecessary Filtering 121
7.2 Related Works 121
7.3 A VLSI Design for Deblocking Filter 122
7.3.1 Subtasks Scheduling 122
7.3.2 Architecture 122
7.3.2.1 Filtering Order 124
7.3.2.2 Memory Organization 125
7.3.2.3 Two-Result-Per-Cycle Edge Filter 125
7.3.2.4 Pixels Transfer of a Non-skip-all MB 127
7.3.3 Evaluation 128
7.4 Summary 130
8 CABAC Encoder 131
8.1 Introduction 131
8.1.1 CABAC Encoder Algorithm 131
8.1.1.1 Building Context Table 132
8.1.1.2 Binarization Schemes 132
8.1.1.3 Context Modeler 135
8.1.1.4 Binary Arithmetic Encoder 136
8.1.1.5 CABAC Encoding Flow 138
8.1.2 Subtasks Processing Order 140
8.1.3 Design Consideration 140
8.2 Related Works 142
8.3 A VLSI Design for CABAC Encoder 145
8.3.1 Subtasks Scheduling 145
8.3.2 Architecture 146
8.3.2.1 BCMODS Generation for Sig_coeff_flag and Last_sig_coeff_flag Types 147
8.3.2.2 BCMODS Generation for Coeff_level Type 147
8.3.2.3 BCMODS Generation for CBF Type 148
8.3.2.4 BCMODS Generation for MVD Type 149
8.3.2.5 Pipelined Multibin BAE Architecture 149
8.3.3 Evaluation 153
8.4 Summary 154
9 System Integration 157
9.1 Introduction 157
9.1.1 Algorithm 157
9.1.2 Design Consideration 159
9.2 Related Works 161
9.3 A VLSI Design for H.264/AVC Encoder 162
9.3.1 Subtasks Scheduling 162
9.3.2 Architecture 165
9.3.2.1 Encoder Core 166
9.3.2.2 AMBA Interface 168
9.3.3 Evaluation 171
9.4 Summary 172
References 173
Index 178
| Erscheint lt. Verlag | 29.12.2009 |
|---|---|
| Zusatzinfo | XI, 176 p. |
| Verlagsort | New York |
| Sprache | englisch |
| Themenwelt | Mathematik / Informatik ► Informatik ► Grafik / Design |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | Architectural Design for Video • Cinoression • Filter • H.264/AVC • High Definition Video • Integrated circuit • Low Power Video • Motion Compensator • Motion Estimator • MPEG-4 • Real-time video • video coding • VLSI Design for Video |
| ISBN-10 | 1-4419-0959-1 / 1441909591 |
| ISBN-13 | 978-1-4419-0959-6 / 9781441909596 |
| Haben Sie eine Frage zum Produkt? |
PDF (Wasserzeichen)Größe: 30,5 MB
DRM: Digitales Wasserzeichen
Dieses eBook enthält ein digitales Wasserzeichen und ist damit für Sie personalisiert. Bei einer missbräuchlichen Weitergabe des eBooks an Dritte ist eine Rückverfolgung an die Quelle möglich.
Dateiformat: PDF (Portable Document Format)
Mit einem festen Seitenlayout eignet sich die PDF besonders für Fachbücher mit Spalten, Tabellen und Abbildungen. Eine PDF kann auf fast allen Geräten angezeigt werden, ist aber für kleine Displays (Smartphone, eReader) nur eingeschränkt geeignet.
Systemvoraussetzungen:
PC/Mac: Mit einem PC oder Mac können Sie dieses eBook lesen. Sie benötigen dafür einen PDF-Viewer - z.B. den Adobe Reader oder Adobe Digital Editions.
eReader: Dieses eBook kann mit (fast) allen eBook-Readern gelesen werden. Mit dem amazon-Kindle ist es aber nicht kompatibel.
Smartphone/Tablet: Egal ob Apple oder Android, dieses eBook können Sie lesen. Sie benötigen dafür einen PDF-Viewer - z.B. die kostenlose Adobe Digital Editions-App.
Zusätzliches Feature: Online Lesen
Dieses eBook können Sie zusätzlich zum Download auch online im Webbrowser lesen.
Buying eBooks from abroad
For tax law reasons we can sell eBooks just within Germany and Switzerland. Regrettably we cannot fulfill eBook-orders from other countries.
aus dem Bereich
