Dynamic Reconfigurable Architectures and Transparent Optimization Techniques (eBook)

Preface 6
Acknowledgements 8
Contents 9
Acronyms 13
Introduction 16
Challenges 16
Main Motivations 19
Overcoming Some Limits of the Parallelism 19
Taking Advantage of Combinational and Reconfigurable Logic 21
Software Compatibility and Reuse of Existent Binary Code 22
Increasing Yield and Reducing Manufacture Costs 23
This Book 25
References 25
Reconfigurable Systems 27
Introduction 27
Basic Principles 29
Reconfiguration Steps 29
Underlying Execution Mechanism 31
Advantages of Using Reconfigurable Logic 34
Application 36
An Instruction Merging Example 36
Reconfigurable Logic Classification 38
Code Analysis and Transformation 38
RU Coupling 39
Granularity 41
Instruction Types 43
Reconfigurability 44
Directions 44
Heterogeneous Behavior of the Applications 45
Potential for Using Fine Grained Reconfigurable Arrays 48
Coarse Grain Reconfigurable Architectures 52
Comparing Both Granularities 55
References 57
Deployment of Reconfigurable Systems 59
Introduction 59
Examples of Reconfigurable Architectures 60
Chimaera 60
RU Coupling 60
Reconfigurable System and Granularity 60
Instruction Type, Reconfiguration and Execution 61
Code Analysis and Transformation 62
Evaluation 62
GARP 63
RU Coupling 63
Granularity 63
Reconfigurable System 63
Instruction Type, Reconfiguration and Execution 64
Code Analysis and Transformation 65
Evaluation 65
REMARC 66
RU Coupling 66
Reconfigurable System and Granularity 66
Instruction Type, Reconfiguration and Execution 68
Code Analysis and Transformation 69
Evaluation 69
Rapid 69
RU Coupling, Reconfigurable System and Granularity 69
Instruction Type, Reconfiguration and Execution 70
Code Analysis and Transformation 70
Evaluation 70
Piperench (1999) 71
RU Coupling 71
Reconfigurable System and Granularity 71
Instruction Type, Reconfiguration and Execution 73
Code Analysis and Transformation 74
Evaluation 74
Molen 75
RU Coupling, Reconfigurable System and Granularity 75
Instruction Type, Reconfiguration and Execution 75
Code Analysis and Transformation 76
Evaluation 76
Morphosys 77
RU Coupling, Reconfigurable System and Granularity 77
Instruction Type, Reconfiguration and Execution 79
Code Analysis and Transformation 79
Evaluation 79
ADRES 80
RU Coupling 80
Reconfigurable System, Granularity, Instruction Type, Reconfiguration and Execution 80
Code Analysis and Transformation 81
Evaluation 81
Concise 82
RU Coupling and Granularity 82
Reconfigurable System, Instruction Type, Reconfiguration and Execution 82
Code Analysis and Transformation 83
Evaluation 83
PACT-XPP 83
RU Coupling 84
Reconfigurable System, Granularity, Instruction Type 84
Reconfiguration and Execution 85
Code Analysis and Transformation 86
Evaluation 86
RAW 87
RU Coupling 87
Reconfigurable System and Granularity 87
Instruction Type, Reconfiguration and Execution 88
Code Analysis and Transformation 88
Evaluation 88
Onechip 89
RU Coupling 89
Reconfigurable System and Granularity 89
Code Analysis and Transformation 90
Instruction Type, Reconfiguration and Execution 90
Evaluation 90
Chess 90
RU Coupling, Reconfigurable System, Granularity, Instruction Type, Reconfiguration and Execution 90
Code Analysis and Transformation, and Evaluation 92
PRISM I 92
RU Coupling, Reconfigurable System, Granularity, Instruction Type, Reconfiguration and Execution 92
Code Analysis and Transformation 92
Evaluation 92
PRISM II 92
RU Coupling 93
Reconfigurable System, Granularity, Instruction Type, Reconfiguration and Execution 93
Code Analysis and Transformation 94
Evaluation 94
Nano 94
RU Coupling 94
Reconfigurable System, Granularity, Instruction Type, Reconfiguration and Execution 94
Code Analysis and Transformation 95
Evaluation 95
Recent Dataflow Architectures 95
Summary and Comparative Tables 97
Other Reconfigurable Architectures 97
Benchmarks 98
References 103
Dynamic Optimization Techniques 108
Introduction 108
Binary Translation 108
Main Motivations 108
Basic Concepts 110
Challenges 112
Register Mapping 112
Memory Mapped I/O 112
Atomic Instructions 112
Issues Related to the Code 113
OS Emulation 113
Examples 113
DAISY 115
VEST 116
DYNAMO 118
Transmeta Crusoe 119
FX!32 120
Reuse 122
Instruction Reuse 122
Value Prediction 123
Block Reuse 124
Trace Reuse 125
Dynamic Trace Memoization and RST 127
References 128
Dynamic Detection and Reconfiguration 131
Warp Processing 131
The Reconfigurable Array 132
How Translation Works 133
Evaluation 135
Configurable Compute Array 136
The Reconfigurable Array 136
Instruction Translator 137
Evaluation 140
Drawbacks 140
References 141
The DIM Reconfigurable System 143
Introduction 143
General System Overview 145
The Reconfigurable Array in Details 146
Translation, Reconfiguration and Execution 147
The BT Algorithm in Details 150
Data Structure 150
How It Works 151
Additional Extensions 152
Handling False Dependencies 154
Speculative Execution 155
Case Studies 157
Coupling the Array to a Superscalar Processor 157
Coupling the Array to the MIPS R3000 Processor 161
Final Considerations 166
DIM in Stack Machines 167
On-Going and Future Works 168
First Studies on the Ideal Shape of the Reconfigurable Array 168
Sleep Transistors 170
Speculation of Variable Length 171
DSP, SIMD and Other Extensions 171
Design Space to Be Explored 171
References 171
Conclusions and Future Trends 174
Introduction 174
Decreasing the Routing Area of Reconfigurable Systems 174
Measuring the Impact of the OS in Reconfigurable Systems 176
Reconfigurable Systems to Increase the Yield 177
Study of the Area Overhead with Technology Scaling and Future Technologies 178
Scheduling Targeting to Low-power 179
Granularity-Comparisons 179
Reconfigurable Systems Attacking Different Levels of Instruction Granularity 179
Multithreading 179
CMP 181
Final Considerations 183
References 183
Index 185