Substrate Noise Coupling in RFICs (eBook)

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2008 | 2008
XV, 119 Seiten
Springer Netherland (Verlag)
978-1-4020-8166-8 (ISBN)

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Substrate Noise Coupling in RFICs - Ahmed Helmy, Mohammed Ismail
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The book reports modeling and simulation techniques for substrate noise coupling effects in RFICs and introduces isolation structures and design guides to mitigate such effects with the ultimate goal of enhancing the yield of RF and mixed signal SoCs. The book further reports silicon measurements, and new test and noise isolation structures. To the authors' knowledge, this is the first title devoted to the topic of substrate noise coupling in RFICs as part of a large SoC.



Mohammed Ismail is the Springer Series Advisor for the Analog Circuits and Signal Processing book series
Substrate noise coupling in integrated circuits (ICs) is the process by which int- ference signals in the form of voltage and current glitches cause parasitic currents to ?ow in the silicon substrate to various parts of the IC. The source of such glitches and parasitic currents could be from the switching noise of high speed digital clocks on the same chip. In RF and mixed signal ICs the switching noise is coupled to sensitive analog and RF nodes in the IC causing degradation in performance that could severely impact the yield. Thus, overcoming substrate coupling is a key issue in successful "e;system on chip"e; ?rst-pass integration where RF and mixed signal blocks, high speed digital I/O interface are integrated with digital signal proce- ing algorithms on the same chip. This is particularly true as we move to sub-90 nanometer system on chip integration. In this book a substrate aware design ?ow is built, calibrated to silicon and used as part of the design and validation ?ows to uncover and ?x substrate coupling problems in RF ICs. The ?ow is used to develop a comprehensive RF substrate noise isolation design guide to be used by RF designers during the ?oor planning, circuit design and validation phases. This will allow designers to optimize the - sign, maximize noise isolation and protect sensitive analog/RF blocks from being degraded by substrate noise coupling.

Mohammed Ismail is the Springer Series Advisor for the Analog Circuits and Signal Processing book series

Abstract. Dedication. Acknowledgements. Vita. List of Tables. List of Figures. Chapter 1. Introduction. Motivation and Research Objectives. Contributions Thesis Organization. Chapter 2. Analysis of Substrate Noise Coupling. Process Regions. Process cross sections. Connection of devices to the substrate. Devices directly connected to the substrate network. Devices indirectly connected to the substrate network. Noise coupling mechanism. Substrate Noise Injection Mechanisms. Substrate Noise Reception Mechanisms. Substrate Noise Transmission Mechanisms. Substrate doping profile tradeoffs. Substrate Model extraction in the IC design flow. Doping Profile Considerations. Substrate model extraction kernels. Finite Difference method. Boundary Element method. Comparison between the two Techniques. Approximations in the Model Extraction Algorithm. Conclusion. Chapter 3. Experimental Data to calibrate the design flow. Introduction. The test chip. Baseline Isolation. Data analysis. Effect of p-guard ring on isolation. Data analysis. Effect of n-guard ring on isolation. Data analysis. Effect of deep n-well on isolation. Data analysis. Effect of deep trench on isolation. Data analysis. De-embedding. Conclusion. Chapter 4. Design Guide for Substrate Noise Isolation for RF Applications Introduction. Isolation in Low resistivity substrate. Isolation vs. Frequency for different isolation structures. Effect of back plane connection on the noise isolation in high resistivity substrates. Substrate Contacts: Front side or Backside? Both. P+ Guard Ring Isolation. Guard Ring Isolation vs. D. Guard Ring grounding scheme. Guard Ring Isolation vs. d. Guard Ring Isolation vs. 'w'. P+ and N+ Guard Rings Isolation. Floor planning techniques to minimize coupling. Circuit techniques to minimize coupling. Active guard rings. Conclusion. Chapter 5. On Chip Inductor Design Flow. Introduction. Integrated Inductors. Inductor Design Flow. Analytical exploration of the design space. Inductor Model and Substrate Parasitics. Calibrating the field solver. Model fit. DFM effects. Impact of bumps. Impact of temperature variation. Impact of process variation. Impact of metal fill. Conclusion. Chapter 6. Case studies for the impact and remedy of substrate noise coupling. Introduction. System Level Case study. Background. Design Data. Block Level Case study. Design details. Device Level Case study. Conclusion. Chapter 7. Conclusion and Future work. Appendix A Scattering Parameters. Appendix B Measurements Setup. Bibliography.

Erscheint lt. Verlag 23.3.2008
Reihe/Serie Analog Circuits and Signal Processing
Analog Circuits and Signal Processing
Zusatzinfo XV, 119 p.
Verlagsort Dordrecht
Sprache englisch
Themenwelt Technik Elektrotechnik / Energietechnik
Technik Nachrichtentechnik
Schlagworte algorithm • Circuit • Integrated circuit • RF and mixed signal ICs • Simulation • SoC • Substrate Noise • System on chip (SoC) • Tables
ISBN-10 1-4020-8166-9 / 1402081669
ISBN-13 978-1-4020-8166-8 / 9781402081668
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