Digital System Designs and Practices

Ming-Bo Lin is a Professor of Electronic Engineering at National Taiwan University of Science and Technology, and has served as adjunct Professor at National Taiwan University. He has been teaching Computer Engineering and Microelectronics for over twenty years. Lin's research interests include VLSI system design, mixed-signal integrated circuit designs, parallel architectures and algorithms, and embedded computer systems. He has published over forty journal and conference papers in these areas. In addition, Lin has directed the designs of over thirty ASICs and has consulted in industry extensively in the fields of ASIC, SoC, and embedded system designs. During the past twenty years, he has translated two books and authored over ten books in Traditional Chinese. Lin holds a B.Sc.degree in Electronic Engineering from the National Taiwan Institute of Technology, an M.Sc.degree in Electrical Engineering from National Taiwan University, and a Ph.D. in Electrical Engineering from the University of Maryland, College Park.

PREFACE. CHAPTER 1 INTRODUCTION. 1.1 Introduction. 1.2 Introduction to Verilog. 1.3 Module Modeling Styles. 1.4 Simulation. CHAPTER 2 STRUCTURAL MODELING. 2.1 Gate-Level Modeling. 2.2 Gate Delays. 2.3 Hazards. 2.4 Switch-Level Modeling. CHAPTER 3 DATAFLOW MODELING. 3.1 Dataflow Modeling. 3.2 Operands. 3.3 Operators. CHAPTER 4 BEHAVIORAL MODELING. 4.1 Procedural Constructs. 4.2 Procedural Assignments. 4.3 Timing Control. 4.4 Selection Statements. 4.5 Iterative (Loop) Statements. CHAPTER 5 TASKS, FUNCTIONS AND UDPS. 5.1 Tasks. 5.2 Functions. 5.3 System Tasks and Functions. 5.4 User-Defined Primitives. CHAPTER 6 HIERARCHICAL STRUCTURAL MODELING. 6.1 Module. 6.2 generate Statement. 6.3 Configurations. CHAPTER 7 ADVANCED MODELING TECHNIQUES. 7.1 Sequential and Parallel Blocks. 7.2 Procedural Continuous Assignments. 7.3 Delay Models and Timing Checks. 7.4 Compiler Directives. CHAPTER 8 COMBINATIONAL LOGIC MODULES. 8.1 Decoders. 8.2 Encoders. 8.3 Multiplexers. 8.4 Demultiplexers. 8.5 Magnitude Comparators. 8.6 A Case Study: Seven-Segment LED Display. CHAPTER 9 SEQUENTIAL LOGIC MODULES. 9.1 Flip-Flops. 9.2 Memory Elements. 9.3 Shift Registers. 9.4 Counters. 9.5 Sequence Generators. 9.6 Timing Generators. CHAPTER 10 DESIGN OPTIONS OF DIGITAL SYSTEMS. 10.1 Design Options of Digital Systems. 10.2 PLD Modeling. 10.3 CPLD. 10.4 FPGA. 10.5 Practical Issues. 11 SYSTEM DESIGN METHODOLOGY. 11.1 Finite-State Machine. 11.2 RTL Design. 11.3 RTL Implementation Options. 11.4 A Case Study: Liquid-Crystal Displays. CHAPTER 12 SYNTHESIS. 12.1 Design Flow of ASICs and FPGA-Based Systems. 12.2 Design Environment and Constraints. 12.3 Logic Synthesis. 12.4 Language Structure Synthesis. 12.5 Coding Guidelines. CHAPTER 13 VERIFICATION. 13.1 Functional Verification. 13.2 Simulation. 13.3 Test Bench Design. 13.4 Dynamic Timing Analysis. 13.5 Static Timing Analysis. 13.6 Value Change Dump (VCD) Files. 13.7 A Case Study: FPGA-Based Design and Verification Flow. CHAPTER 14 ARITHMETIC MODULES. 14.1 Addition and Subtraction. 14.2 Multiplication. 14.3 Division. 14.4 Arithmetic and Logic Unit. 14.5 Digital-Signal Processing Modules. CHAPTER 15 DESIGN EXAMPLES. 15.1 Bus. 15.2 Data Transfer. 15.3 General-Purpose Input and Output. 15.4 Timers. 15.5 Universal Asynchronous Receiver and Transmitter. 15.6 A Simple CPU Design. 16 DESIGN FOR TESTABILITY. 16.1 Fault Models. 16.2 Test Vector Generation. 16.3 Testable Circuit Design. 16.4 System-Level Testing. APPENDIX A VERILOG HDL SYNTAX. A.1 Keywords. A.2 Source Syntax. A.3 Declarations. A.4 Primitive Instances. A.5 Module and Generated Instantiation. A.6 UDP Declaration and Instantiation. A.7 Behavioral Statements. A.8 Specify Section. A.9 Expressions. A.10 General. INDEX.