High-Speed Signaling

Kyung Suk (Dan) Oh received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Illinois, Urbana-Champaign, in 1990, 1992, and 1995, respectively. His doctoral research was in the area of computational electromagnetics applied to transmission line modeling and simulation. He is a Senior Principal Engineer at Rambus Inc. He leads signal integrity analysis for various products including serial, parallel, and memory interfaces. He is also responsible for developing advanced signal and power integrity analysis tools. His current interests include advance signal and power integrity modeling and simulation techniques, optimization of channel designs for various standard or proprietary I/O links, and application of signaling techniques to high-speed digital links.      Dr. Oh has published more than 80 papers and holds 7 issued U.S. patents and 10 pending patent applications in areas of high-speed link design. He received two Best Paper Awards in DesignCon and 2008 Best Paper Award in the IEEE Advanced Packaging journal. Dr. Oh serves on the technical program committee of IEEE EPEPS, and is a former member of the IEC DesignCon Technical Program Committee.      Xingchao (Chuck) Yuan received his B.S. degree in Electronic Engineering from Nanjing Institute of Technology (now Southeast University), Nanjing, China, in 1982. He received both his M.S. and Ph.D. degrees in Electrical Engineering from Syracuse University, Syracuse, New York, in 1983 and 1987, respectively. After receiving his Ph.D., Dr. Yuan was at the Thayer School of Engineering at Dartmouth College; first as a Postdoctoral fellow, and later as a Research Assistant Professor from 1987 to 1990.      From 1990 to 1995, Dr. Yuan was employed by Ansoft Corp., where he led the development of Ansoft’s flagship product HFSSTM (High Frequency Structure Simulator). His work led to three different product releases, which included features such as modeling conductor and dielectric loss, radiation and periodic boundary conditions for modeling antennas, and electromagnetic scattering/interference problems. He pioneered a fast frequency sweep method that combined a finite element method and an asymptotic waveform evaluation method. This led to a dramatic speed improvement in the speed of 3D full-wave modeling. From 1995 to 1998, Dr. Yuan was with Cadence Corp. where he led the research and development of the signal integrity and EMI tools. His work focused on modeling SSO noise and induced electromagnetic interference, which led to some of the earliest research in power plane modeling.      Since 1998, Dr. Yuan has been with Rambus Inc, Sunnyvale, California, as a director of signal integrity engineering. Dr Yuan is responsible for designing, modeling, and implementing Rambus multi-gigahertz signaling technologies using conventional interconnect technologies. His technical and managerial leadership at Rambus has led to an industry-recognized signal and power integrity team of experts. Rambus’ SI/PI papers are closely followed by the rest of the industry, and represent the latest developments in high-performance signal and power integrity modeling and design. Dr. Yuan’s team was among the first to apply BER and statistical methodology to memory interface designs, and to explore the relationship between the supply noise spectrum and the jitter spectrum. His team’s work led to the successful development of Rambus’ XDR memory architecture, which was adopted by PlayStation 3, DLP projectors, and DTVs. Since 2009, Dr. Yuan has served as an engineering director in charge of a silicon team with dozens of engineers (in both the U.S. and India) who are responsible for designing next-generation Rambus graphics and main memory interfaces. In 2010, the team taped out a multi-modal PHY that explores the limits of single-ended signaling beyond 12.8Gbps, a power efficient differential interface at 20Gbps, and backward compatibility with existing memory interfaces (including GDDR5 and DDR3).      Dr. Yuan has authored more than 100 papers in technical journals and conferences and holds 8 issued U.S. patents. He is a senior member of IEEE, and served on the technical program committee of IEEE EPEPS from 2008 to 2009.

Preface     viii
Chapter 1 Introduction     1
1.1 Signal Integrity Analysis Trends     4
1.2 Challenges of High-Speed Signal Integrity Design     8
1.3 Organization of This Book     9
References     11
Chapter 2 High-Speed Signaling Basics     13
2.1 I/O Signaling Basics and Components     13
2.2 Noise Sources     24
2.3 Jitter Basics and Decompositions     33
2.4 Summary     39
References     39
Part I Channel Modeling and Design     41
Chapter 3 Channel Modeling and Design Methodology     43
3.1 Channel Design Methodology     44
3.2 Channel Modeling Methodology     49
3.3 Modeling with Electromagnetic Field Solvers     52
3.4 Backplane Channel Modeling Example     54
3.5 Summary     63
References     64
Chapter 4 Network Parameters     65
4.1 Generalized Network Parameters for Multi-Conductor Systems     66
4.2 Preparing an Accurate S-Parameter Time-Domain Model     77
4.3 Passivity Conditions     85
4.4 Causality Conditions     89
4.5 Summary     98
References     101
Chapter 5 Transmission Lines     103
5.1 Transmission Line Theory     104
5.2 Forward and Backward Crosstalk    109
5.3 Time-Domain Simulation of Transmission Lines    115
5.4 Modeling Transmission Line from Measurements     121
5.5 On-Chip Wire Modeling    136
5.6 Comparison of On-Chip, Package, and PCB Traces     142
5.7 Summary     145
References     145
Part II Analyzing Link Performance    151
Chapter 6 Channel Voltage and Timing Budget    153
6.1 Timing Budget Equation and Components     155
6.2 Fibre Channel Dual-Dirac Model     156
6.3 Component-Level Timing Budget    160
6.4 Pitfalls of Timing Budget Equation     161
6.5 Voltage Budget Equations and Components    164
6.6 Summary     165
References     165
Chapter 7 Manufacturing Variation Modeling     167
7.1 Introduction to the Taguchi Method    168
7.2 DDR DRAM Command/Address Channel Example    179
7.3 Backplane Link Modeling Example    186
7.4 Summary     192
7.5 Appendix     193
References     196
Chapter 8 Link BER Modeling and Simulation    197
8.1 Historical Background and Chapter Organization    198
8.2 Statistical Link BER Modeling Framework    199
8.3 Intersymbol Interference Modeling     206
8.4 Transmitter and Receiver Jitter Modeling    210
8.5 Periodic Jitter Modeling     218
8.6 Summary    225
References    226
Chapter 9 Fast Time-Domain Channel Simulation Techniques     229
9.1 Fast Time-Domain Simulation Flow Overview     230
9.2 Fast System Simulation Techniques     232
9.3 Simultaneous Switching Noise Example     245
9.4 Comparison of Jitter Modeling Methods    246
9.5 Peak Distortion Analysis    248
9.6 Summary    253
References    253
Chapter 10 Clock Models in Link BER Analysis    257
10.1 Independent and Common Clock Jitter Models     258
10.2 Modeling Common Clocking Schemes     259
10.3 CDR Circuitry Modeling     268
10.4 Passive Channel JIF and Jitter Amplification     273
10.5 Summary     277
References     277
Part III Supply Noise and Jitter     279
Chapter 11 Overview of Power Integrity Engineering     281
11.1 PDN Design Goals and Supply Budget     282
11.2 Power Supply Budget Components     283
11.3 Deriving a Power Supply Budget     287
11.4 Supply Noise Analysis Methodology     290
11.5 Steps in Power Supply Noise Analysis     294
11.6 Summary     300
References     301
Chapter 12 SSN Modeling and Simulation     303
12.1 SSN Modeling Challenges     305
12.2 SI and PI Co-Simulation Methodology     310
12.3 Signal Current Loop and Supply Noise     321
12.4 Additional SSN Modeling Topics     325
12.5 Case Study: DDR2 SSN Analysis for Consumer Applications     330
12.6 Summary     336
References     337
Chapter 13 SSN Reduction Codes and Signaling     339
13.1 Data Bus Inversion Code     340
13.2 Pseudo Differential Signaling Based on 4b6b Code     346
13.3 Summary     357
References     357
Chapter 14 Supply Noise and Jitter Characterization     359
14.1 Importance of Supply Noise Induced Jitter     360
14.2 Overview of PSIJ Modeling Methodology     361
14.3 Noise and Jitter Simulation Methodology     364
14.4 Case Study     372
14.5 Summary     376
References     377
Chapter 15 Substrate Noise Induced Jitter     379
15.1 Introduction     380
15.2 Modeling Techniques     382
15.3 Measurement Techniques     391
15.4 Case Study     393
15.5 Summary     400
References     400
Part IV Advanced Topics     403
Chapter 16 On-Chip Link Measurement Techniques     405
16.1 Shmoo and BER Eye Diagram Measurements     407
16.2 Capturing Signal Waveforms     408
16.3 Link Performance Measurement and Correlation     411
16.4 On-Chip Supply Noise Measurement Techniques     412
16.5 Advanced Power Integrity Measurements     418
16.6 Summary     422
References     423
Chapter 17 Signal Conditioning     425
17.1 Single-Bit Response     426
17.2 Equalization Techniques     427
17.3 Equalization Adaptation Algorithms     433
17.4 CDR and Equalization Adaptation Interaction     442
17.5 ADC-Based Receive Equalization     445
17.6 Future of High-Speed Wireline Equalization     448
17.7 Summary     449
References     450
Chapter 18 Applications     455
18.1 XDR: High-Performance Differential Memory System     456
18.2 Mobile XDR: Low Power Differential Memory System     465
18.3 Main Memory Systems beyond DDR3     476
18.4 Future Signaling Systems     486
References     491
Index     495