Variation Tolerant On-Chip Interconnects
Seiten
2011
Springer-Verlag New York Inc.
978-1-4614-0130-8 (ISBN)
Springer-Verlag New York Inc.
978-1-4614-0130-8 (ISBN)
This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.
Introduction.- Interconnect Design Techniques.- On-Chip Wire Modeling.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.
Introduction.- On-Chip Communication.- Interconnect Design Techniques.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.
| Reihe/Serie | Analog Circuits and Signal Processing |
|---|---|
| Zusatzinfo | XII, 172 p. |
| Verlagsort | New York, NY |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 1-4614-0130-5 / 1461401305 |
| ISBN-13 | 978-1-4614-0130-8 / 9781461401308 |
| Zustand | Neuware |
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