Low-Voltage Low-Power Digital BiCMOS Circuits
Prentice Hall (Verlag)
978-0-13-011380-1 (ISBN)
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1138K-9 Low-Voltage, Low-Power Digital BiCMOS Circuits Circuit Design, Comparative Study and Sensitivity Analysis Innovative techniques for low-voltage, minimum power BiCMOS design State-of-the-art BiCMOS design techniques are critical to delivering the low-voltage, minimum-power, maximum-performance circuits demanded by today's highest value applications. This comprehensive review of the field focuses on the latest design concepts, in-depth analyses, and methodologies-all fully supported by experimental data, and illuminated by the insights of two world-recognized experts. The authors introduce the fundamentals of low-voltage, low-power design, with a comprehensive description of BiCMOS process technology that highlights techniques for maximizing performance. They present a new low-power ultra-low capacitance BiCMOS process, and preview other key trends in BiCMOS process technology.
Comprehensive coverage also includes: * A new methodology for constructing a device model for a given wafer, using device characterization tools and experimental data * Analytical and experimental characterization of sub-half micron MOS devices * Full-swing BiCMOS circuits, bootstrapping, and transient saturation * Quasi-Complementary BiCMOS, Schottky BiCMOS/BiNMOS, high-beta BiCMOS, and feedback BiCMOS circuits-including the latest advances * Comparative evaluations of how leading BiCMOS circuits are currently applied in low-voltage, low-power environments The book offers exceptionally thorough coverage of predicting and managing BiCMOS circuit delay time and power dissipation sensitivities. In particular, it offers a convenient, reliable solution for calculating worst-case speed degradation given a set of device and process parameter tolerances. For every professional moving towards lower power, higher performance circuits, Low-Voltage, Low-Power Digital BiCMOS Circuits will be an essential resource.
SAMIR S. ROFAIL and KIAT-SENG YEO are members of the faculty at the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. They have published numerous articles on BiCMOS technology in leading technical publications worldwide, and have been selected as reviewers for IEEE, IEE, Electronics Letters, and International Journal of Electronics.
1. Introduction.
Why Low-Voltage, Low-Power? Why BiCMOS Technology? Applications of BiCMOS. Low-Voltage Low-Power Design. Conclusions. References.
2. BiCMOS Process Technology.
Introduction. Bipolar and CMOS Processes Convergence. CMOS Processing Issues of the Twin-Well BiCMOS Process. Bipolar Process Techniques. BiCMOS Isolation Issues. BiCMOS Interconnect Issues. Classification of BiCMOS Technologies. A New Low-Power Ultra Low-Capacitance BiCMOS Process. Manufacturing Considerations. Future Trends in BiCMOS Technology. Conclusions. References.
3. MOS Device Modeling.
The Threshold Voltage Models. The MOSFET Current Models. The MOSFET in a Hybrid Mode Environment. Concluding Remarks. Summary. References.
4. Low-Voltage BiCMOS Digital Circuits.
Introduction. Source-Well Tie and Quasi-Reduction of Bipolar Turn-On Voltage Techniques. Full-Swing BiCMOS Logic Circuits with Complementary Emitter-Follower Driver Configuration. Merged BiCMOS (MBiCMOS) Logic Gates. Full Voltage Swing Multi-Drain/Multi-Collector Complementary BiCMOS Buffers. Quasi-Complementary BiCMOS Logic Circuits. Full-Swing Schottky BiCMOS/BiNMOS Logic Circuits. Feedback-Type BiCMOS Logic Circuits. High-Beta BiCMOS (Hb-BiCMOS) Logic Circuits. Transiently Saturated Full-Swing BiCMOS (TS-FS-BiCMOS) Logic Circuits. Bootstrapped BiCMOS Logic Circuits. References.
5. Delay Time and Power Dissipation Sensitivity Analyses of Multi-Generation BiCMOS Digital Circuits.
Introduction. Relationship Between Key BJT/MOS Process and Device/Circuit Parameters. Sensitivity Analysis of the Conventional BiCMOS Circuit. Sensitivity Evaluation and Comparison of Low-Voltage, Low-Power BiCMOS Circuits. Delay Sensitivity Upper and Lower Bounds: A Worst Case Scenario. Conclusions. References. Appendix. The Authors.
Index.
| Erscheint lt. Verlag | 2.9.1999 |
|---|---|
| Verlagsort | Upper Saddle River |
| Sprache | englisch |
| Maße | 185 x 240 mm |
| Gewicht | 778 g |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| Technik ► Nachrichtentechnik | |
| ISBN-10 | 0-13-011380-8 / 0130113808 |
| ISBN-13 | 978-0-13-011380-1 / 9780130113801 |
| Zustand | Neuware |
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