Enabling Techniques for Si Integrated Transceiver Circuits

In this work simplified design and development techniques for Silicon based CMOS and bipolar transceiver circuits operating up to millimeter waves have been presented. An electromagnetic analysis based circuit development is emphasized for successful implementations. At first a study based on the field solvers is made on the on-chip electromagnetic coupling due to passive elements particularly the spiral inductors. The influence of such coupling effects with and without the electromagnetic shielding on the performance of a standard cascode CMOS low noise amplifier is studied and certain important conclusions regarding the RF circuit design flow are derived. The results of this research led to the modification of the conventional method and proposal of a modified design flow. This technique is applied for all the microwave integrated circuit designs presented in this work. From the circuit design aspects, a methodical design procedure exploiting the transistor biasing, scaling and critical design parameters is proposed for the implementation of a two stage common-emitter bipolar LNA operating in 6 GHz band. It will be shown that by following the proposed design techniques, excellent results are achievable for bipolar LNAs in 6 GHz range. Similarly, a systematic and algorithmic approach for the design of a cascode CMOS LNA in 5 GHz band is also proposed and state-of-the-art performance are achieved for cascode CMOS LNAs in 5 GHz range. To satisfy the targeted project requirements, both the bipolar and CMOS LNA designs are extended to form a fully integrated single-to-differential LNAs using transformer based balun at the output. The single-to-differential LNAs are then integrated with other circuits to form various versions of the targeted high performance FMCW radar receiver. A comparative study has been made between a cascode CMOS LNA and a cascode bipolar LNA in 5 GHz band. It will be shown that under the same power consumption a cascode CMOS achieves a higher figure of merit compared to its bipolar counter-part. All of the above implementations are made in 0.18 μm SiGe BiCMOS process. The remaining part of this work focuses on 60 GHz wireless systems with emphasize on the circuit design and realization of a 60 GHz downconverter and layout design aspects of a 60 GHz power amplifier. A high performance 0.25 μm SiGe BiCMOS process has been used for the realization of all the mm-Wave frequency circuits. A single balanced mixer with push-pull balun is chosen for the downconverter implementation. The fully integrated downconverter achieves high linearity, wide-band RF performance, conversion gain, with very low power consumption. In each and every implementation, the measured results are compared to the published state-of-the-art performance. The layout analysis of the 60 GHz PA is made on the two different layout versions of a single power amplifier circuit. Important conclusions related to the arrangement of transistor layouts in the power stage are derived. The ability to estimate the measured results for both the layout versions using the EM based design flow gives a great scope for the future enhancement and optimization of this method to simplify the complete mm-Wave Si based transceivers.