Power Supply Integrity in Low Power Designs

Power supply integrity has emerged as a serious challenge for integrated circuit design over the last decades. In the following work, power supply noise in low power integrated circuits will be discussed.

The work starts by outlining the basics of power supply distribution, on-chip and offchip, and the source of power supply distortions will be described. A scaling scenario shows that power supply noise will increase by a factor of up to 2.5× within the next two technology generations, if no countermeasures are taken. Special focus is laid on the implications of low power design in contrast to high performance design.

The basic challenge of power supply noise analysis is laid out and a methodology for estimating the impact of on-chip inductance is presented. With product related show cases it is shown, that on-chip inductance has no impact on the timing of circuits, since the timing critical metric, the cycle average of the supply voltage, is not affected.