On-Chip Inductive Interconnects

With the decrease in feature size of CMOS integrated
circuits, interconnect design has become an
important issue in high speed, high complexity
integrated circuits. Different design methodologies
have been proposed to improve circuit performance.
Wire sizing, driver sizing, repeater insertion, and
wire shaping are common techniques to enhance
circuit performance.
With increasing signal frequencies and the
corresponding decrease in signal transition times,
the interconnect impedance can behave inductively.
Line inductance introduces new tradeoffs in
interconnect design and driver sizing to decrease
the circuit delay. Different design methodologies
under an inductive environment are described in this
book. Including line inductance in the design
process can enhance both the delay and power as well
as improve the accuracy of the overall design
process. By including the on-chip inductance, the
efficiency of different circuit design techniques
such as wire sizing, driver sizing, repeater
insertion, and line tapering can be greatly
enhanced.