High Frequency Interconnect Characterization and Modeling

Continuous scaling of transistors combined with
increased chip area results in the ratio of global
wire delay to gate delay increasing at a super-linear
rate. Simple RC models have become inadequate for
simulation of VLSI circuits. In addition, parasitic
inductance and capacitance of IC packages impose
limits on the circuit performance at RF frequencies.
This book presents modeling of on-chip inductance for
chips with ground grids that emulate those used in
real circuits. S-parameter characterization of test
chips up to 10 GHz shows good agreement with
simulation and analytical calculations. On-chip 3-D
capacitance modeling capabilities for arbitrarily
shaped objects are also presented. In addition, an
approach to fast 3-D modeling of the geometry for
bonding wires in RF circuits and packages is
demonstrated. The geometry and an equivalent circuit
are presented to model the frequency response of
bonding wires. Excellent agreement between modeled
results and measured data is achieved for frequencies
up to 10 GHz. The book should be useful to the
semiconductor professionals in academia and industry,
who are interested in the on-chip and package
interconnects researches.