Low Power Design for Microprocessors and System on Chip

Reducing on-chip power consumption has become a critical challenge for System-on-Chip (SOC) designers in the nanotechnology era. This book contains an industry perspective on low power design focusing on the deep sub-micron designs needed to achieve the functionality/low-power needs.

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In highly mobile, frequently wireless applications like cell phones, the trend is towards smaller and lighter weight packaging yet with increasing functionality and lower price. The demand from end users for increased battery service life is considerable. Reducing on-chip power consumption has become a critical challenge for System-on-Chip (SOC) designers. A new way of thinking about Low power will be necessary to succeed in the consumer electronics arena going forward. Low power design techniques will be used from the earliest phase of the design cycle to have the maximum impact on power convergence and optimization.

As Lead Engineers for Intel and Marvell, respectively, Subhomoy Chattopadhyay and Rakesh Patel work daily at the leading edge of R&D on low power design. This book contains an industry perspective on low power design not currently available, with its focus on the deep sub-micron designs currently needed to achieve the functionality/low-power needs described above.