Electronic Design Automation (eBook)

Front Cover 1
Electronic Design Automation: Synthesis, Verification, and Test 4
Copyright Page 5
Contents 6
Preface 22
In the Classroom 26
Acknowledgments 28
Contributors 30
About the Editors 34
CHAPTER 1 Introduction 38
1.1 Overview of electronic design automation 39
1.2 Logic design automation 50
1.3 Test automation 55
1.4 Physical design automation 62
1.5 Concluding remarks 69
1.6 Exercises 70
Acknowledgments 72
References 72
CHAPTER 2 Fundamentals of CMOS design 76
2.1 Introduction 76
2.2 Integrated circuit technology 77
2.3 CMOS logic 86
2.4 Integrated circuit design techniques 95
2.5 CMOS physical design 108
2.6 Low-power circuit design techniques 121
2.7 Concluding remarks 129
2.8 Exercises 129
Acknowledgments 132
References 132
CHAPTER 3 Design for testability 134
3.1 Introduction 135
3.2 Testability analysis 137
3.3 Scan design 146
3.4 Logic built-in self-test 155
3.5 Test Compression 176
3.6 Concluding remarks 198
3.7 Exercises 199
Acknowledgments 202
References 202
CHAPTER 4 Fundamentals of algorithms 210
4.1 Introduction 210
4.2 Computational complexity 212
4.3 Graph algorithms 222
4.4 Heuristic algorithms 245
4.5 Mathematical programming 258
4.6 Concluding remarks 267
4.7 Exercises 267
Acknowledgments 269
References 269
CHAPTER 5 Electronic system-level design and high-level synthesis 272
5.1 Introduction 273
5.2 Fundamentals of High-level synthesis 283
5.3 High-level synthesis algorithm overview 298
5.4 Scheduling 300
5.5 Register binding 310
5.6 Functional unit binding 318
5.7 Concluding remarks 326
5.8 Exercises 330
Acknowledgments 331
References 331
CHAPTER 6 Logic synthesis in a nutshell 336
6.1 Introduction 336
6.2 Data Structures for Boolean representation and reasoning 339
6.3 Combinational logic minimization 369
6.4 Technology mapping 399
6.5 Timing analysis 408
6.6 Timing optimization 421
6.7 Concluding remarks 429
6.8 Exercises 430
Acknowledgments 437
References 437
CHAPTER 7 Test synthesis 442
7.1 Introduction 443
7.2 Scan design 445
7.3 Logic built-in self-test (BIST) design. 462
7.4 RTL Design for testability 475
7.5 Concluding remarks 480
7.6 Exercises 480
Acknowledgments 483
References 483
CHAPTER 8 Logic and circuit simulation 486
8.1 Introduction 487
8.2 Logic simulation models 490
8.3 Logic simulation techniques 496
8.4 Hardware-accelerated logic simulation 502
8.5 Circuit simulation models 512
8.6 Numerical methods for transient analysis 517
8.7 Simulation of VLSI interconnects 522
8.8 Simulation of nonlinear devices 532
8.9 Concluding remarks 541
8.10 Exercises 543
Acknowledgments 546
References 547
CHAPTER 9 Functional verification 550
9.1 Introduction 551
9.2 Verification hierarchy 552
9.3 Measuring verification quality 557
9.4 Simulation-based approach 569
9.5 Formal approaches 577
9.6 Advanced research 598
9.7 Concluding remarks 600
9.8 Exercises 601
Acknowledgments 607
References 607
CHAPTER 10 Floorplanning 612
10.1 Introduction 612
10.2 Simulated annealing approach 617
10.3 Analytical approach 644
10.4 Modern floorplanning considerations 649
10.5 Concluding remarks 662
10.6 Exercises 662
Acknowledgments 668
References 668
CHAPTER 11 Placement 672
11.1 Introduction 672
11.2 Problem formulations 674
11.3 Global placement: partitioning-based approach 678
11.4 Global placement: simulated annealing approach 686
11.5 Global placement: analytical approach 690
11.6 Legalization 711
11.7 Detailed placement 712
11.8 Concluding Remarks 716
11.9 Exercises 717
Acknowledgments 719
References 719
CHAPTER 12 Global and detailed routing 724
12.1 Introduction 725
12.2 Problem definition 726
12.3 General-purpose routing 729
12.4 Global routing 734
12.5 Detailed Routing 741
12.6 Modern routing considerations 752
12.7 Concluding remarks 775
12.8 Exercises 777
Acknowledgments 782
References 782
CHAPTER 13 Synthesis of clock and power/ground networks 788
13.1 Introduction 788
13.2 Design considerations 790
13.3 Clock Network design 800
13.4 Power/ground network design 866
13.5 Concluding remarks 880
13.6 Exercises 880
Acknowledgments 883
References 883
CHAPTER 14 Fault Simulation and Test Generation 888
14.1 Introduction 888
14.2 Fault Collapsing 891
14.3 Fault Simulation 898
14.4 Test Generation 913
14.5 Advanced Test Generation 939
14.6 Concluding Remarks 946
14.7 Exercises 947
Acknowledgments 950
References 950
Index 956