Digital Frequency Synthesis Demystified (eBook)

Front Cover 1
Digital Frequency Synthesis Demystified: DDS and Fractional-N PLLs 2
Copyright Page 3
Contents 6
Prefaces 12
Symbols 16
Chapter 1. Introduction to Frequency Synthesis 18
1-1 Introduction and Definitions 18
1-2 Synthesizer Parameters 22
1-3 Auxiliary Specifications 30
1-4 Review of Synthesis Techniques 30
1-5 Comparative Analysis 52
1-6 Conclusion 54
References 55
Chapter 2. Frequency Synthesizer System Analysis 56
2-1 Multiplying and Dividing 56
2-2 Phase Noise 59
2-3 Spurious and Phase Noise in PLL 66
2-4 Phase Noise Mechanism 68
2-5 Mixing and Filtering 70
2-6 Frequency Planning 72
References 73
Chapter 3. Measurement Techniques 74
3-1 Switching Speed 74
3-2 Phase Noise 78
3-3 Phase Continuity 83
3-4 Spurious Signals (Especially DDS) 84
3-5 Phase Memory 86
3-6 Step Size 86
3-7 Linear FM 87
3-8 Conclusion 87
References 88
Chapter 4. DDS General Architecture 90
4-1 Digital Modulators and Signal Reconstruction 92
4-2 Pulse Output DDS of the First Order 99
4-3 Pulse Output DDS of the Second Order 104
4-4 Standard DDS 106
4-5 Randomization 122
4-6 Quantization Errors 126
4-7 Logic Speed Considerations 137
4-8 Modulation 137
4-9 State-of-the-Art Components and Systems 145
4-10 Performance Evaluation 150
4-11 Sample-and-Hold Devices 151
4-12 Single-Bit DDS Revisited 152
4-13 Arbitrary Waveform Generators 155
4-14 Digital Chirp DDS 157
4-15 Conclusion 158
Appendix 4A DDS Applications 158
Appendix 4B DDS—Spectra and the Time Domain 160
Appendix 4C Sampling Theorem 174
Appendix 4D The Effect of Phase Noise on Data Conversion Devices 176
References 177
Chapter 5. Phase-Locked Loop Synthesizers 180
5-1 Main Components of PLL Synthesis 181
5-2 Performance Evaluation 201
5-3 Fractional-N Synthesizers 218
5-4 Fractlonal-N Synthesis of the Third Order 237
5-5 DDS-Based PLL 241
5-6 Single-Chip PLL Synthesis 244
5-7 Conclusion 247
References 252
Chapter 6. Accumulators 254
6-1 Binary Accumulators 254
6-2 Decimal Accumulators 262
6-3 Interface to ROM 263
6-4 Accumulator DDS 265
6-5 Phase Adder and Accumulator Segmentation 265
6-6 Conclusion 267
References 267
Chapter 7. Lookup Table and Sine ROM Compression 268
7-1 ROM Algorithm 269
7-2 Quadrant Compression 273
7-3 Compression Principles 276
7-4 Direct Taylor Approximation 277
7-5 Hutchison Algorithm 279
7-6 Sundarland Algorithm 283
7-7 Variations and Randomization 286
7-8 Auxiliary Function ROM Approximation 288
7-9 Coordinate Transformation (CORDIC) 292
7-10 Other Methods 295
7-11 Conclusion 296
References 297
Chapter 8. Digital-to-Analog Converters 298
8-1 DAC Performance Evaluation 299
8-2 DAC Principles of Operation 302
8-3 DAC Parameters 309
8-4 State-of-the-Art DACs 313
8-5 Sine-Wave DAC 316
8-6 Multiplexing 316
References 320
Chapter 9. Synthesizers in Use and Reference Generators 322
9-1 Synthesizers in Use 322
9-2 Reference Generators 330
9-3 Conclusion 336
References 336
Chapter 10. Original Paper and Software 338
10-1 Tierney, Rader, and Gold Article 338
10-2 Software Description 339
Index 350