See MIPS Run (eBook)

Front Cover 1
See MIPS® Run 4
Copyright Page 5
Contents 8
Foreword 6
Preface 16
Style and Limits 19
Conventions 19
Acknowledgments 20
Chapter 1. RISCs and MIPS Architectures 22
1.1 Pipelines 23
1.2 The MIPS Five-Stage Pipeline 26
1.3 RISC and CISC 28
1.4 Great MIPS Chips of the Past and Present 29
1.5 MIPS Compared with CISC Architectures 44
Chapter 2. MIPS Architecture 50
2.1 A Flavor of MIPS Assembly Language 54
2.2 Registers 55
2.3 Integer Multiply Unit and Registers 59
2.4 Loading and Storing: Addressing Modes 60
2.5 Data Types in Memory and Registers 60
2.6 Synthesized Instructions in Assembly Language 63
2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions 64
2.8 Basic Address Space 68
2.9 Pipeline Visibility 71
Chapter 3. Coprocessor 0: MIPS Processor Control 74
3.1 CPU Control Instructions 76
3.2 Which Registers Are RelevantWhen? 79
3.3 CPU Control Registers and Their Encoding 80
3.4 CP0 Hazards—A Trap for the Unwary 96
Chapter 4. How CachesWork on MIPS Processors 100
4.1 Caches and Cache Management 100
4.2 How CachesWork 101
4.3 Write-Through Caches in Early MIPS CPUs 104
4.4 Write-Back Caches in MIPS CPUs 104
4.5 Other Choices in Cache Design 105
4.6 Managing Caches 106
4.7 L2 and L3 Caches 109
4.8 Cache Configurations for MIPS CPUs 109
4.9 Programming MIPS32/64 Caches 111
4.10 Cache Efficiency 119
4.11 Reorganizing Software to Influence Cache Efficiency 121
4.12 Cache Aliases 123
Chapter 5. Exceptions, Interrupts, and Initialization 126
5.1 Precise Exceptions 128
5.2 When Exceptions Happen 130
5.3 Exception Vectors:Where Exception Handling Starts 130
5.4 Exception Handling: Basics 134
5.5 Returning from an Exception 135
5.6 Nesting Exceptions 135
5.7 An Exception Routine 136
5.8 Interrupts 136
5.9 Starting Up 145
5.10 Emulating Instructions 149
Chapter 6. Low-level Memory Management and the TLB 152
6.1 The TLB/MMU Hardware andWhat It Does 152
6.2 TLB/MMU Registers Described 153
6.3 TLB/MMU Control Instructions 161
6.4 Programming the TLB 162
6.5 Hardware-Friendly Page Tables and Refill Mechanism 164
6.6 Everyday Use of the MIPS TLB 168
6.7 Memory Management in a Simpler OS 170
Chapter 7. Floating-Point Support 172
7.1 A Basic Description of Floating Point 172
7.2 The IEEE 754 Standard and Its Background 173
7.3 How IEEE Floating-Point Numbers Are Stored 175
7.4 MIPS Implementation of IEEE 754 179
7.5 Floating-Point Registers 180
7.6 Floating-Point Exceptions/Interrupts 182
7.7 Floating-Point Control: The Control/Status Register 182
7.8 Floating-Point Implementation Register 186
7.9 Guide to FP Instructions 187
7.10 Paired-Single Floating-Point Instructions and the MIPS-3D ASE 194
7.11 Instruction Timing Requirements 200
7.12 Instruction Timing for Speed 200
7.13 Initialization and Enabling on Demand 201
7.14 Floating-Point Emulation 202
Chapter 8. Complete Guide to the MIPS Instruction Set 204
8.1 A Simple Example 204
8.2 Assembly Instructions andWhat They Mean 206
8.3 Floating-Point Instructions 231
8.4 Differences in MIPS32/64 Release 1 237
8.5 Peculiar Instructions and Their Purposes 239
8.6 Instruction Encodings 254
8.7 Instructions by Functional Group 273
Chapter 9. Reading MIPS Assembly Language 284
9.1 A Simple Example 285
9.2 Syntax Overview 289
9.3 General Rules for Instructions 290
9.4 Addressing Modes 292
9.5 Object File and Memory Layout 295
Chapter 10. Porting Software to the MIPS Architecture 300
10.1 Low-Level Software for MIPS Applications: A Checklist of Frequently Encountered Problems 301
10.2 Endianness:Words, Bytes, and Bit Order 302
10.3 Trouble with Visible Caches 317
10.4 Memory Access Ordering and Reordering 322
10.5 Writing it in C 326
Chapter 11. MIPS Software Standards (ABIs) 332
11.1 Data Representations and Alignment 333
11.2 Argument Passing and Stack Conventions for MIPS ABIs 340
Chapter 12. Debugging MIPS Designs—Debug and Profiling Features 360
12.1 The “EJTAG” On-chip Debug Unit 362
12.2 Pre-EJTAG Debug Support—Break Instruction and CP0 Watchpoints 379
12.3 PDtrace 380
12.4 Performance Counters 381
Chapter 13. GNU/Linux from Eight Miles High 384
13.1 Components 385
13.2 Layering in the Kernel 389
Chapter 14. How Hardware and SoftwareWork Together 392
14.1 The Life and Times of an Interrupt 392
14.2 Threads, Critical Regions, and Atomicity 396
14.3 What Happens on a System Call 399
14.4 How Addresses Get Translated in Linux/MIPS Systems 401
Chapter 15. MIPS Specific Issues in the Linux Kernel 420
15.1 Explicit Cache Management 420
15.2 CP0 Pipeline Hazards 424
15.3 Multiprocessor Systems and Coherent Caches 424
15.4 Demon Tweaks for a Critical Routine 427
Chapter 16. Linux Application Code, PIC, and Libraries 430
16.1 How Link Units Get into a Program 432
16.2 Global Offset Table (GOT) Organization 433
Appendix A. MIPS Multithreading 436
A.1 What Is Multithreading? 436
A.2 Why Is MT Useful? 438
A.3 How to Do Multithreading for MIPS 438
A.4 MT in Action 442
Appendix B. Other Optional Extensions to the MIPS Instruction Set 446
B.1 MIPS16 and MIPS16e ASEs 446
B.2 The MIPS DSP ASE 449
B.3 The MDMX ASE 450
MIPS Glossary 452
References 498
Books and Articles 498
Online Resources 499
Index 502