Recent Advances in PMOS Negative Bias Temperature Instability

Souvik Mahapatra received his Bachelors and Masters degrees in Physics from Jadavpur University, Calcutta, India in 1993 and 1995 respectively, and PhD in Electrical Engineering from IIT Bombay, Mumbai, India in 1999. During 2000-2001, he was with Bell Laboratories, Lucent Technolgies, Murray Hill, NJ, USA. Since 2002 he is with IIT Bombay, and is currently the PK Kelkar Chair Professor in the Department of Electrical Engineering. His primary research interests are in the areas of semiconductor device characterization, modeling and simulation, and in particular, MOS transistor and Flash memory device scaling and reliability. He has interacted closely with major semiconductor industries in the world, and has contributed in several technologically relevant research topics such as MOS gate insulator scaling, Bias Temperature Instability and Hot Carrier Degradation in CMOS devices, CHISEL NOR Flash, SONOS NOR and NAND Flash memory devices. He has authored and co-authored more than 190 papers in peer reviewed journals and conferences and several book chapters, and delivered invited talks and tutorials in major international conferences around the world, including at the IEEE IEDM and IEEE IRPS. He has served as a distinguished lecturer of the IEEE EDS, chair of the IEEE EDS device reliability physics subcommittee, and in paper selection subcommittees and as session chairs in several IEEE conferences. He is a fellow of Institute of Electrical and Electronics Engineers (IEEE), Indian National Science Academy (INSA), Indian National Academy of Engineering (INAE) and Indian Academy of Sciences (IASc).

Characterization of NBTI Parametric Drift.- BAT Framework Modeling of Gate First HKMG Si and SiGe Channel FDSOI MOSFETs.- BTI Analysis Tool (BAT) Model Framework.- BAT Framework Modeling of RMG HKMG SOI FinFETs.- BAT Framework Modeling of RMG HKMG GAA-SNS FETs.- BAT Framework Modeling of RMG HKMG Si and SiGe Channel FinFETs.- BAT Framework Modeling of Gate First HKMG Si Channel MOSFETs.- BAT Framework Modeling of AC NBTI: Stress Mode, Duty Cycle and Frequency.- BAT Framework Modeling of Dimension Scaling in FinFETs and GAA-SNS FETs.- BTI Analysis Tool (BAT) Model Framework – Generation of Interface Traps.- Device Architecture, Material and Process Dependencies of NBTI Parametric Drift.- Physical Mechanism of NBTI Parametric Drift.- BAT Framework Modeling of Gate First HKMG Si-capped SiGe Channel MOSFETs.- BTI Analysis Tool (BAT) Model Framework – Interface Trap Occupancy and Hole Trapping.