Three-Dimensional Integration of Semiconductors (eBook)

Kazuo Kondo is Professor at Department of Chemical engineering, Osaka Prefecture University. He took his PhD in Chemical Engineering at the University of Illinois in 1981. He has worked for Sumitomo Metal Industries, Hokkaido University and Okayama University. He has 200 research publications and 100 patents. His major research is Copper Electrodeposition for TSV. His research extends in various fields not only in electrodeposition, but also in battery and CVD. He is member of Electrochemical Society, IEEE, Society of Chemical engineering Japan, Japanese Institute of Electronics Packaging, Surface Finishing Society of Japan, Materia Japan, Electrochemistry Japan and Japanese Society of Applied Physics.  Morihiro Kada is the invited researcher of The National Institute of Advanced Industrial Science and Technology (AIST) and the part-time researcher of Osaka Prefecture University. Prior to joining to AIST and the university he was the consultant of Association of Super-Advanced Electronics Technologies (ASET). Since April 2007 he has been heading the Japanese national R&D project on 3D-Integration technology as the Project in ASET. Before joining to ASET, he had been the General Manager of the Advanced Packaging Development Department in Sharp Corporation. He has more than forty years experience in semiconductor packaging engineering, with major emphasis on developing chip scale, chip stack package and Three Dimensional-System in Package (3D-SiP) as the pioneer of 3D-Integration technology in the world.Kenji Takahashi is a Chief Specialist at Memory Packaging Development Department, Memory Division, Semiconductor & Strage Company, Toshiba Corporation. He received a M.E. Degree of from Chemical Engineering at the University of Tokyo in 1984 and Ph.D. from Information Science and Electrical Engineering at Kyushu University in 2010. His major research and development is focused on semiconductor packaging and chip package interaction, especially through-silicon via technology. He was the Research Manager of Electronic System Integration Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET). He is a Senior Member of IEEE, a member of Society for Chemical Engineers, Japan, Institute of Electronics, Information and Communication Engineers and Japanese Institute of Electronics Packaging.

Chapter 1 - Research and Development History of Three Dimensional (3D) Integration Technology
1.1Introduction
1.1.1The International Technology Roadmap for Semiconductors
1.1.2Three-dimensional Integration Technology
1.2Motivation for 3D Integration Technology y
1.3Research and Development History of 3D Integration Technology R&D History of 3D Packaging Technology
1.3.13D Packaging Technology
1.3.2Origin of the TSV Concept
1.3.3Research and Development History of 3D Technology in Organizations
1.3.3.1Japan
1.3.3.2Japanese 3D Integration Technology Research and Development Project (Dream Chip)
1.3.3.3USA
1.3.3.4Europe
1.3.3.5Asia
1.3.3.6International
1.4Research and Development History of 3D Integration Technology for Applications
1.4.1CMOS Image Sensor and MEMS
1.4.2DRAM
1.4.32.5D with Interposer
1.4.4Others

Chapter 2- Recent Research and Development Activities of Three Dimensional (3D) Integration Technology
2.1Recent Announcement of Research and Development Activities
2.2Dynamic Random-Access Memory (DRAM)
2.2.1Through-Silicon Via (TSV) Technology for DRAM
2.2.2Wide I/O and Wide I/O2 Mobile DRAM
2.3Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) DRAM
2.3.1Hybrid Memory Cube (HMC)High Bandwidth Memory (HBM) DRAM
2.3.2High Bandwidth Memory (HBM) DRAM
2.4FPGA and 2.5D
2.5Others
2.6New Energy and Industrial Technology Development Organization (NEDO) Japan
2.6.1Next Generation “Smart Device” Project
2.6.2Background, Purpose and Target of “Smart Device” Project

Chapter 3- TSV Processes
3.1Deep Silicon Etching by Bosch process
3.1.1Introduction
3.1.2Basic characteristics of the Bosch process
3.1.3Bosch Etching Equipment for TSV
3.1.4Conclusions
3.2High Rate Silicon-Via Etching and Basics of Sidewall Etch Reaction by Steady-State Etch Process
3.2.1Introduction
3.2.2MERIE Process for TSV Application
3.2.2.1Effect of RF Frequency
3.2.2.2Effect of Pressure
3.2.2.3Effect of Oxygen Addition
3.2.3Investigation of Sidewall Etch Reaction Induced by SF6/O2 Plasma
3.2.3.1Effect of Oxygen Addition
3.2.3.2Effect of Temperature
3.2.3.3Effect of SiF4 Addition
3.2.4Conclusion
3.3Low Temperature CVD Technology
3.3.1Introduction
3.3.2Cathode-Coupled PECVD (LS-CVD)
3.3.3Low Temperature SiO2 Deposition
3.3.3.1Wafer Temperature During Low Temperature Deposition
3.3.3.2Step Coverage in Si Via Holes
3.3.3.3Electrical Characteristics of SiO2 Film Deposited at Low Temperature
3.3.3.4Stress Control of SiO2 Film Deposited Using LS-CVD
3.3.4Conclusion
3.4Electrodeposition for Via-Filling
3.4.1Cu+ Ion as an Accelerant Additive of Copper Electrodeposition
3.4.2Relation between via Filling and Cu+ Ion by Periodical Reverse Current Waveform
3.4.3Simulation of Cu+ Ion Distribution inside the Via
3.4.4High Speed via Filling Electrodeposition by Other Organizations
3.4.5Reduction of Thermal Expansion Coefficient of Electrodeposited Copper for TSV by Additive

Chapter 4 - Wafer Handling and Thinning Processes
4.1Wafer Thinning Solution for TSV Devices
4.1.1Introduction
4.1.2General Thinning
4.1.3Wafer Thinning for TSV devices
4.1.4TTV control
4.1.5Summary
4.2A Novel Via Middle TSV Thinning Technology by Si/Cu Grinding and CMP
4.2.1Introduction
4.2.2Methods
4.2.3Results and Discussion
4.2.3.1Si/Cu Same Rate CMP (1st CMP)
4.2.3.2TSV Protrusion CMP (2nd CMP)
4.2.3.3Post CMP Cleaning after 2nd CMP
4.2.4Conclusion
4.3Temporally Bonding
4.3.1Background
4.3.2The 3MTM Temporary Bonding Materials
4.3.3The 3MTM Temporary Adhesive
4.3.4Laser Absorbing Layer
4.3.5The Next Steps
4.4Temporary Bonding and Debonding for Through-Silicon Via (TSV) Processing
4.4.1Introduction
4.4.2Temporary Bonding and Debonding Process
4.4.3Debonding Method
4.4.4Functions and Performance Requirements for Temporary Bonding Device
4.4.5Ability and Performance Requirements for Debonding Devices
4.4.6Tokyo Electron’s Temporary Bonder and Debonder Device Concept and Lineup
4.4.7Future Outlook

Chapter 5- Wafer and Die Bonding Processes
5.1Permanent Wafer Bonding
5.1.1Introduction
5.1.2Low Temperature or Room Temperature Wafer Direct Bonding Method and Application
5.1.2.1Fusion Bonding
5.1.2.2Surface Activated Bonding
5.1.2.3Anodic Bonding
5.1.2.4Cu2Cu/Oxide Hybrid bonding
5.1.2.5Conclusion of Low Temperature or Room Temperature Wafer Direct Bonding Methods and Their Applications
5.1.2.6Future Outlook for Bonding Application Using Low Temperature or Normal Room Temperature Wafer Direct Bonding Methods
5.1.3Requests Made to Equipment Makers and Initiatives Regarding Low Temperature or Room Temperature Wafer Direct Bonding Methods
5.1.3.1Post BAA
5.1.3.2Scaling
5.1.3.3Distortion
5.1.3.4Bonding strength
5.1.3.5Void
5.1.4Tokyo Electron Initiatives
5.1.5Conclusion
5.2Underfill Materials
5.2.1Technical Trend for Three Dimensional Integration Packages and Underfill Materials
5.2.2Requirements for Underfill Materials
5.2.2.1Requirements for CUF and Material Technology Trend
5.2.2.2Requirements for NCP and Material Technology Trend
5.2.3 Application to CUF between the Stacked Chips
5.3Non-Conductive Films
5.3.1Introduction
5.3.2Required Material Feature from Bonding Process
5.3.3Voiding Issue in NC
5.3.4High Through Put NCF-TCB

Chapter 6- Metrology and Inspection
6.1Principles of Spectroscopic Reflectometry
6.1.1Introduction
6.1.2Measurement
6.1.3Setup
6.1.4Analysis
6.1.5Conclusion
6.2Low Coherence Interferometry for 3D-IC TSV
6.2.1Optical Measurement of Topographies and Thicknesses
6.2.1.13D-IC TSV Needs Tomography
6.2.1.2Tomography with Low Coherence Interferometry
6.2.2Theory of Optical Coherence Tomography
6.2.2.1Basic Principle
6.2.2.2Time Domain OCT
6.2.2.3Fourier Domain OCT
6.2.3Practical Considerations
6.2.4Conclusion
6.3Silicon and Glue Thickness Measurement for Grinding
6.3.1Introduction
6.3.2TSV Wafer Manufacturing Method and Challenges of Grinding
6.3.3Features of BGM300
6.3.4Verifying BGM300 Measurement Results
6.3.5Measurement after Grinding
6.3.6Optimized wafer Grinding Based on Via Height Information from BGM300
6.3.7Conclusion
6.43D X-ray Microscopy Technology for Non-Destructive Analysis of Through-Silicon Vias
6.4.1Introduction
6.4.2Fundamentals of X-ray Microscopy
6.4.2.1Physics of X-ray Imaging
6.4.2.23D X-ray Microscopy
6.4.3Applications for TSV Process Development
6.4.4Applications for TSV Failure Analysis
6.4.5Summary
6.5Wafer Warpage and Local Distortion Measurement
6.5.1Introduction
6.5.2Basic Functions of WDM300
6.5.3Measurement and Analysis of Local Deformations
6.5.4Application
6.5.5Summary

Chapter 7 - TSV Characteristics and Reliability: Impact of 3D Integration Processes on Device Reliability
7.1Introduction
7.2Impact of Cu Contamination on Device Reliabilities in Thinned 3D-IC Chip
7.2.1Impact of Cu Diffusion at Backside Surface in Thinned 3D-IC Chip
7.2.1.1Effect of Intrinsic Gettering (IG) layer
7.2.1.2Effect of Extrinsic Gettering (EG) layer
7.2.2Impact of Cu Diffusion from Cu Via
7.2.2.1Effect of the Barrier Thickness and the Scallop Roughness
7.2.2.2Effect of the Annealing Temperature
7.2.2.3Keep Out Zone (KOZ) Characterization by Cu Diffusion from Cu Via
7.3Impact of Mechanical Stress/Strain on Device Reliability in Stacked IC
7.3.1Micro-Bump Induced Local Stress in Stacked IC
7.3.2Si Mechanical Strength Reduction by Thinning
7.4Impact of 3D Integration Process on DRAM Retention Characteristics
7.4.1Impact of Mechanical Strength on Retention Characteristics in Thinn DRAM Chip
7.4.2Impact of Cu Contamination on Memory Retention Characteristics in DRAM Chip

Chapter 8 - Trends in 3D Integrated Circuit (3D-IC) Testing Technology
8.1Crucial Issues and Key Technologies for 3D-IC Testing
8.2Research Trends in Pre-bond Test for 3D-IC
8.3Research Trends in Post-bond Test for 3D-IC
8.4Research Trends in Automatic Test Pattern Generator (ATPG) and Test Scheduling for TSVs in 3D-IC
8.5An Accurate Resistance Measuring Method for TSVs in 3D-IC
8.5.1Background of Our Study
8.5.2Problems of Conventional Analog Boundary-Scan for TSV Resistance Measurement
8.5.2.1Analog Boundary-Scan
8.5.2.2Standard resistance measuring method by 1149.4
8.5.2.3Problems of conventional Analog Boundary-Scan for TSV resistance measuring
8.5.3Proposed Measuring Method
8.5.3.1Floating Measurement method
8.5.3.2Complete isolation of the current path and the voltage path
8.5.3.3Segmenting the internal analog BUS (AB1, AB2)
8.5.4Summary
8.6Delay Measurement Circuits for Detecting TSV Delay Faults
8.6.1Application of Time-to-Digital Converter Embedded in Boundary-Scan for 3D-IC Testing
8.6.2Delay Measurement Circuit Using the Vernier Delay Line
8.6.3Estimation of Defect Size Detectable by the Test Method
8.6.4Summary
8.7Electrical Interconnect Tests of Open Defects in a 3D-IC with a Built-in Supply Current Test Circuit
8.7.1Electrical Tests with a Built-in Supply Current Test Circuit
8.7.2Experimental Evaluation of Our Electrical Test Method
8.7.3Summary

Chapter 9 - Dream Chip Project at ASET
9.1Overview of Japanese 3D Integration Technology R&D Project (Dream Chip)
9.2Thermal Management and Chip Stacking Technology
9.2.1Background
9.2.2Chip Stacking/Joining Technology
9.2.2.1Metal Bump Materials and Structure
9.2.2.2Reliability Study of Micro Bump
9.2.2.3Electro Migration Test to Understand Current Density of Micro Bump Joint
9.2.2.4Flip Chip Bonding Density Towards 10 μm Connection Bump Pitch
9.2.2.5Stack and Gang Bonding
9.2.2.6Non-destructive Inspection Technologies of Micro Joint
9.2.3Thermal Management Study
9.2.3.1Evaluation Technology of 3D Integrated Chip Stack
9.2.3.2TV200 Measurement Result and Correlation with Simulation
9.2.3.3Thermal Conductivity Anisotropy Induced by Cu TSV
9.2.4Development of Automobile Drive Assistance Camera
9.2.4.1Development of Integration Process
9.2.4.2Development of Cooling System for Automobile Drive Assistance Camera
9.2.5Summery
9.3Thin Wafer Technology
9.3.1Back Ground of Wafer Thinning Technology
9.3.2Issues of Wafer Thinning
9.3.3Ultrathin Wafer Thinning Process
9.3.3.1Wafer Support System (WSS)
9.3.3.2Thermal Resistance of the Resin Used for WSS Temporary Bonding
9.3.3.3Dicing Technology of Thin Chip
9.3.3.4Die Pick-up Technology of Thin Chip
9.3.3.5Thin Wafer Processing Technique in the Wafer Stacking Process
9.3.4Issues on Wafer Thinning to Prevent Device Characteristics Change and Metal Contamination
9.3.4.1Evaluation Method of a Crystal Defect and Metal Pollution in the Thin Wafer
9.3.4.2Backside Grinding Methods and Their EG Effect
9.3.4.3Electrical Characteristics Deviation by Mechanical Stress
9.3.5Standardization
9.3.6Summary
9.43D Integration Technology
9.4.1Background and Scope
9.4.2C2C Process
9.4.2.1C2C Integration Overview
9.4.2.2C2C Integration Results
9.4.3W2W Process
9.4.3.1W2W Integration Overview
9.4.3.2Wafer Bonding Technology
9.4.3.3W2W Integration Results
9.4.4Summary
9.5Ultra-wide Bus 3D-System-in Package (3D-SiP) Technology
9.5.1Background
9.5.2The Test Vehicle Fabrication
9.5.3Evaluation
9.5.4Summary
9.6Mixed Signal (Digital and Analog) 3D Integration Technology for Automotive Application
9.6.1Introduction
9.6.2Challenges
9.6.3Result of Basic Technology Development on Mixed-Signal 3D Integration Technology
9.6.3.1Basic Technology Development on 3D Integrated Imaging Sensor Module for In-Vehicle
9.6.3.2Realization of Mixed-Signal (CIS/CDS/ADC/IF) Integrated Structure by TSV Connection
9.6.3.3Development of Si Interposer Which Allotted TSV Type Decoupling Capacitor
9.6.3.4A Trial production and Evaluation of Car Drive Assist Image Processing System for Cars
9.6.4Conclusion
9.7Heterogeneous 3D Integration Technology for Radio Frequency Micro Electro Mechanical Systems RF MEMS (RF MEMS)
9.7.1Background and Issues
9.7.2Development Result
9.7.2.1Structure of 3D integration RF Module
9.7.2.2MEMS Tunable Filter
9.7.2.3MEMS Switch
9.7.2.4CMOS Driving IC
9.7.2.53D Integration of Tunable Filter Module
9.7.2.6RF and Tuning Performances of the Fabricated 3D Tunable Filter Module
9.7.3Summary