Broadband Opto-Electrical Receivers in Standard CMOS (eBook)

Prof. Michiel Steyaert has (co-)authored numerous books for Springer, all are "typical" monographs which have sold well.

Preface. List of Abbreviations and Symbols. 1 Introduction. 1.1 A History of Optical Communication. 1.2 Emerging Applications. 1.3 Silicon Opto-Electronics. 1.4 Outline of the Work. 2 Optical Receiver Fundamentals. 2.1 Introduction. 2.2 The Optical Receiver Front-End. 2.2.1 A Transceiver for Optical Communication Systems. 2.2.2 A Pickup Unit for Optical Storage Systems. 2.3 Binary Data Formats. 2.4 Bit Error Rate and Sensitivity. 2.4.1 Bit error rate. 2.4.2 Sensitivity. 2.5 Intersymbol Interference. 2.5.1 Low-Pass Filtering. 2.5.2 High-Pass Filtering. 2.6 Jitter. 2.7 Conclusion. 3 Standard CMOS Photodiodes. 3.1 Introduction. 3.2 Basic Concepts. 3.2.1 Principles of Light Detection. 3.2.2 The Use of Standard CMOS. 3.3 Overview of Published Integrated Photodiodes. 3.3.1 BiCMOS Implementations. 3.3.2 SOI Implementations. 3.3.3 CMOS Implementations. 3.4 One-Dimensional Model. 3.4.1 N-Well P-Substrate Junction. 3.4.2 P+ N-Well Junction with Guard. 3.5 Two-Dimensional Model. 3.5.1 Classical N-Well Diode. 3.5.2 P+ N-Well Diode with Guard. 3.5.3 Differential N-Well Diode. 3.5.4 Influence of Wavelength. 3.5.5 Influence of Technology Scaling. 3.6 Conclusion. 4 Transimpedance Amplifier Design. 4.1 Introduction. 4.2 Performance Requirements. 4.3 Design of the Shunt-Shunt Feedback TIA. 4.3.1 Transimpedance Gain and Bandwidth. 4.3.2 Open-Loop Gain and Loop Gain. 4.3.3 Noise. 4.4 Literature Examples. 4.4.1 Common Source TIA. 4.4.2 Regulated Cascode TIA. 4.4.3 The Latest Trends at ISSCC. 4.5 Case Studies. 4.5.1 An Inverter-Based TIA for Test Photodiodes in 0.18 µm CMOS. 4.5.2 An Inverter-Based TIA for Test Photodiodes in 90 nm CMOS. 4.5.3 A Differential Bandwidth-Optimized TIA in 0.18 µm CMOS. 4.6 Conclusions. 5 Post-Amplifier Design. 5.1 Introduction. 5.2 Performance Requirements. 5.3 Literature Examples. 5.4 Design of a Fully Differential Broadband LA. 5.4.1 Cascaded Gain Stages. 5.4.2 Broadband Cherry-Hooper Stage. 5.4.3 BroadbandStage with Capacitive Source Degeneration. 5.4.4 Offset Compensation. 5.5 Case Studies. 5.5.1 A Four-Stage LA in 0.18 µm CMOS. 5.5.2 A Five-Stage LA with Offset Compensation in 0.18 µm CMOS. 5.6 Conclusions. 6 CMOS Realizations. 6.1 Introduction. 6.2 Test Photodiodes with TIA in 0.18 µm CMOS. 6.2.1 Circuit Description. 6.2.2 Measurements. 6.3 Test Photodiodes with TIA in 90 nm CMOS. 6.3.1 Circuit Description. 6.3.2 Measurements. 6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS. 6.4.1 Circuit Description. 6.4.1.1 Four-Stage Limiting Amplifier. 6.4.1.2 Output Buffer. 6.4.2 Measurements. 6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS. 6.5.1 Circuit Description. 6.5.2 Measurements. 6.6 Conclusions. 7 Conclusions. References. Index.