Regular Nanofabrics in Emerging Technologies (eBook)

Haykel Ben Jamaa is a research engineer at the "Commissariat à l'Energie Atomique et aux Energies Alternatives (CEA-Léti)". He obtained his PhD degree in Electrical Engineering in September 2009 from the "Ecole Polytechnique Fédérale de Lausanne" (EPFL), Switzerland. He received his co-joint MSc degree in Electrical Engineering from the "Technische Universität München", Germany, and the "Ecole Centrale Paris", France, in 2004.He is currently working in the field of nanotechnology with an interdisciplinary approach linking post-CMOS technologies to specific architectures. His research interests include the fabrication techniques for emerging and post-CMOS technologies and non-conventional and fault-tolerant design methodologies and styles for nanometer scale circuits, with a particular emphasis on novel fabrication and design technologies of silicon nanowire crossbar arrays. His expertise consists in linking device fabrication and circuit design; it covers cleanroom processing, device modelling and test, and fault-tolerant circuit design.Previously, he was a visiting researcher at Stanford University, California, USA, a research fellow with the Max-Planck Institute for Solid-State Research in Stuttgart, Germany, and a mixed-signal designer with Infineon Technologies, Munich, Germany. He has been involved in the review process of prestigious conferences and journals (IEEE/ACM Design Automation and Test in Europe Conference - DATE, IEEE Transactions on Computer-Aided Design - TCAD, ACM Journal on Emerging Technologies in Computing Systems - JETC) and he was a TPC member of DATE in 2008, Nano-Net in 2009, NOCS in 2010 and VLSI-SoC in 2010. He obtained the ACM Outstanding Dissertation Award in EDA (2009). Haykel Ben Jamaa also has a MA degree in Finances and Strategy from the "Institut d'Etudes Politiques de Paris", France. He was the president of EPFL's researchers and lecturers association in 2007-2009. He was an elected member of EPFL's School Assembly in 2007-2008. He was also an active member of other communities, such as the PhD Board of EPFL and the humanitarian mission MHIGE.

Acknowledgments 5
Contents 6
List of Acronyms 10
Reference 13
List of Symbols 14
1 Introduction 19
1.1 The Linear Scaling 22
1.2 The Latest Milestones 24
1.2.1 Fabrication Technology 24
1.2.2 Device Design 26
1.2.2.1 Electrostatic Channel Control 26
1.2.2.2 Carrier Mobility 26
1.2.2.3 Leakage 27
1.2.2.4 Gate Stack 27
1.2.2.5 Access Resistance 27
1.2.2.6 Variability 28
1.2.3 System Design 29
1.2.4 Design Tools 30
1.3 Emerging Technologies 31
1.3.1 Selecting Emerging Technologies 32
1.3.2 CMOS Extensions 32
1.3.2.1 Low Dimensional Structures 32
1.3.2.2 High Mobility Materials 34
1.3.3 Novel Information Processing Technologies 34
1.3.3.1 Single-Electron Transistors 34
1.3.3.2 Molecular Devices 35
1.3.3.3 Spin Devices 36
1.4 Regular Architectures and Fabrics 36
1.4.1 The Need for Regularity 37
1.4.2 CMOS Many-Core Architectures 38
1.4.3 Via Patterned Gate Arrays 39
1.4.4 Crossbar Architecture 39
1.4.5 NanoPLA 40
1.4.6 CMOS/Molecular Hybrid Systems 41
1.5 Challenges of Regular Emerging Architectures 42
1.5.1 SiNW Technology 42
1.5.2 CNT Technology 44
1.6 Organization of the Book 45
References 46
2 Fabrication of Nanowire Crossbars 50
2.1 Nanowire Fabrication Techniques 51
2.1.1 Bottom-up Techniques 51
2.1.1.1 Vapor-Liquid-Solid Growth 51
2.1.1.2 Laser-Assisted Catalytic Growth 52
2.1.1.3 Chemical Vapor Deposition 52
2.1.1.4 Opportunities and Challenges of Bottom-up Approaches 52
2.1.2 Top-Down Techniques 54
2.1.2.1 Standard Photolithography Techniques 55
2.1.2.2 Miscellaneous Mask-Based Techniques 55
2.1.2.3 Spacer Techniques 56
2.1.2.4 Nanomold-Based Techniques 56
2.1.2.5 Opportunities and Challenges of Top-Down Approaches 57
2.2 Crossbar Technologies 58
2.2.1 Fluid-Directed Assembly 58
2.2.2 Electric-Field-Assisted Assembly 59
2.2.3 Nanomold-Based Nanowire Crossbars 59
2.2.4 Crossbar Switches 60
2.2.5 Comparison Between Crossbar Technologies 60
2.3 Fabrication Facilities at EPFL 61
2.3.1 Photolithography 62
2.3.1.1 Mask Writing 62
2.3.1.2 Photoresist 63
2.3.1.3 Mask Alignment and Exposure 63
2.3.2 Etching 63
2.3.2.1 Anisotropic Plasma Etch 63
2.3.2.2 Isotropic Plasma Etch 64
2.3.2.3 Wet Etch 64
2.3.2.4 Chemical Mechanical Planarization (CMP) 64
2.3.3 Thin Films 64
2.3.4 Wafer Cleaning 65
2.3.5 Process Control 65
2.4 Process Flow 66
2.5 Process Optimization 69
2.5.1 Etch of Sacrificial Layers 69
2.5.2 Spacer Definition 72
2.5.3 Gate Stack 74
2.6 Device Characterization 75
2.6.1 Structural Characterization 75
2.6.2 Electrical Characterization 78
2.7 Potential Applications 82
2.7.1 Crossbar Structures 82
2.7.2 Single Poly-Si Nanowire Memory 82
2.7.3 Memristors 83
2.7.4 Nanowire Decoders 84
2.8 Discussions 85
2.9 Chapter Contributions and Summary 86
References 87
3 Decoder Logic Design 91
3.1 Crossbar Architecture 92
3.2 Decoder and Encoding Types 93
3.2.1 Decoder Design and Fabrication 94
3.2.1.1 Decoders for Differentiated Nanowires 94
3.2.1.2 Decoders for Undifferentiated Nanowires 95
3.2.2 Encoding Schemes 96
3.3 Multi-Valued Logic Encoding 96
3.3.1 Circuit Design with Multi-Valued Logic 97
3.3.2 Semantic of Multi-Valued Logic Addressing 97
3.3.3 Code Construction 100
3.3.3.1 Hot Encoding 100
3.3.3.2 N-ary Reflexive Code 101
3.3.4 Defect Models 102
3.3.4.1 Basic Error Model 103
3.3.4.2 Overall Impact of Variability 104
3.3.5 Errors in the k-Hot Code Space 106
3.3.5.1 Error Types 106
3.3.5.2 Error Type I 107
3.3.5.3 Error Type II 109
3.3.5.4 Immune Code Space 111
3.3.5.5 Unique Covering 111
3.3.6 Errors in the NRC Space 114
3.3.6.1 Error Types 114
3.3.6.2 Error Type I 115
3.3.6.3 Error Type II 115
3.3.6.4 Immune Code Space 116
3.3.6.5 Unique Covering 117
3.3.7 Assumptions of the Simulations 120
3.3.7.1 Assumptions on the Circuits Geometry 120
3.3.7.2 Statistical Assumptions 121
3.3.8 Simulations of the Addressable Code Space 122
3.3.9 Simulations of the Effective Memory Area 125
3.3.9.1 Top-Down Approach: GAA Decoder Based Memories 125
3.3.9.2 Bottom-Up Approach: Axial Decoder Based Memories 126
3.3.9.3 Summary 128
3.4 The MSPT Decoder 129
3.4.1 Design of the Decoder 129
3.4.2 Problem Formulation of MSPT-Based Nanowire Decoder 130
3.4.3 Optimizing Nanowire Codes 133
3.4.3.1 The Gray Code 134
3.4.3.2 Arranged Hot Codes 135
3.4.4 Simulations of the Decoder 135
3.4.4.1 Simulation Platform 135
3.4.4.2 Simulation Results 137
3.5 Discussions 139
3.6 Chapter Contributions and Summary 141
References 141
4 Decoder Test 144
4.1 Necessity of Testing Crossbar Circuits 145
4.1.1 Operation of Crossbar Memories 145
4.1.2 Testing Complexity 146
4.2 Testing Crossbar Circuits 147
4.2.1 Test Method 147
4.2.2 Test Requirements 149
4.3 Perturbative Current Model 151
4.4 Stochastic Current Model 153
4.4.1 Components of the Sensed Signal 154
4.4.2 Distribution of the Useful Signal 154
4.4.3 Distribution of the Defect-Induced Noise 155
4.4.4 Distribution of the Intrinsic Noise 157
4.4.5 Model of the Test Requirements 157
4.5 Model Implementation 158
4.6 Simulation Results 161
4.6.1 General Signal Variation 162
4.6.2 Optimization of the Thresholder Parameters 162
4.6.3 Analysis of Test Quality 164
4.6.4 Exploration of Linearization Error 165
4.7 Discussions 167
4.8 Chapter Contributions and Summary 168
References 169
5 Logic Design with Ambipolar Devices 170
5.1 Logic Circuits with Carbon Nanotubes 171
5.2 Ambipolar CNTFETs 172
5.3 Dynamic Logic with Ambipolar CNTFETs 175
5.4 Static Logic with Ambipolar CNTFETs 176
5.4.1 Transmission-Gate Static Logic Family 177
5.4.2 Alternate CNTFET Families 180
5.5 Multi-Level Logic Synthesis with Static CNTFET Gates 181
5.5.1 Transmission-Gate Static Design 181
5.5.2 Design of Alternative CNTFET Families 182
5.5.3 Library Characterization 182
5.5.4 Logic Synthesis Results 183
5.6 Design of Regular Fabrics 189
5.6.1 Dynamic PLA Architecture 189
5.6.2 Static Regular Fabrics 192
5.7 Dicussions 194
5.8 Chapter Contributions and Summary 195
References 196
6 Conclusions and Future Work 199
6.1 Book Summary and Contributions 199
6.2 Future Work 201
Index 203