Verilog HDL - Joseph Cavanagh

Verilog HDL

Digital Design and Modeling

(Autor)

Buch | Hardcover
918 Seiten
2007
Crc Press Inc (Verlag)
978-1-4200-5154-4 (ISBN)
205,75 inkl. MwSt
Offering a firm foundation in the design of digital systems using Verilog HDL, this book presents the Verilog language together with a wide variety of examples. It describes the different modeling constructs supported by Verilog with numerous examples designed in each chapter.
Emphasizing the detailed design of various Verilog projects, Verilog HDL: Digital Design and Modeling offers students a firm foundation on the subject matter. The textbook presents the complete Verilog language by describing different modeling constructs supported by Verilog and by providing numerous design examples and problems in each chapter. Examples include counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and much more. The text also contains information on synchronous and asynchronous sequential machines, including pulse-mode asynchronous sequential machines.

In addition, it provides descriptions of the design module, the test bench module, the outputs obtained from the simulator, and the waveforms obtained from the simulator illustrating the complete functional operation of the design. Where applicable, a detailed review of the topic's theory is presented together with logic design principles, including state diagrams, Karnaugh maps, equations, and the logic diagram.

Verilog HDL: Digital Design and Modeling is a comprehensive, self-contained, and inclusive textbook that carries all designs through to completion, preparing students to thoroughly understand this popular hardware description language.

Santa Clara University, California, USA

Introduction. Overview. Language Elements. Expressions. Gate-Level Modeling. User-Defined Primitives. Dataflow Modeling. Behavioral Modeling. Structural Modeling. Tasks and Functions. Additional Design Examples. Appendix A: Event Queue. Appendix B: Verilog Project Procedure. Appendix C: Answers to Selected Problems. Index.

Erscheint lt. Verlag 20.2.2007
Zusatzinfo 75 Tables, black and white; 796 Illustrations, black and white
Verlagsort Bosa Roca
Sprache englisch
Maße 178 x 254 mm
Gewicht 1750 g
Themenwelt Mathematik / Informatik Informatik Programmiersprachen / -werkzeuge
Mathematik / Informatik Informatik Theorie / Studium
Technik Elektrotechnik / Energietechnik
Technik Umwelttechnik / Biotechnologie
ISBN-10 1-4200-5154-7 / 1420051547
ISBN-13 978-1-4200-5154-4 / 9781420051544
Zustand Neuware
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