Progress in Computer-Aided VLSI Design, Volume Two

Formal techniques for hardware correctness verification - an introduction; formal techniques for hardware correctness verification - current research activities; place-router for "Sea-of Gates" design style; mutlilayer routing problem; techniques for minimum-area design of IC power; ground nets; timing delay modelling and simulation of digital CMOS circuits; implementation of device models in electronic circuit simulator programs; fault analysis methods and artificial intelligence; syntheses and optimization of multilevel logic; mapping algorithms onto multidimensional systolic arrays.