Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems

lt;p>Behnaz Ranjbar Received the PhD degree with Summa Cum Laude in Computer Science, from Technische Universität Dresden (TUD), Dresden, Germany, in 2022. Currently, he is a research associate at the Chair of Processor Design, TUD, Germany. His current research interests include the design of embedded real-time systems, fault tolerance systems, and power-aware systems.

Akash Kumar is a chaired Professor of Processor Design (with tenure) in the department of Computer Science at Technische Universität Dresden (TUD), Germany. From 2009 to 2015, he was with the Department of Electrical and Computer Engineering, NUS. He received the joint Ph.D. degree in electrical engineering in embedded systems from Eindhoven University of Technology (TU/e) and National University of Singapore (NUS), in 2009; joint Master's degree from TU/e and NUS in 2005 in embedded systems and Bachelor of Computer Engineering degree from NUS in 2002.

His research interests span various aspects of design automation in the context of embedded real-time systems with particular emphasis on reliable, resource-efficient and predictable architectures for embedded systems, including FPGA-based architectures. His research spans across various layers in the system design from hardware design to application analysis. He has published close to 170 articles in premier international conferences and journals in the area of design automation. Together with his research group, he has released many open-source tool flows for system design and analysis to allow the community to reproduce their results and to further research in the related areas.

He serves (or has recently served) on the program committee of renowned conferences in the area like DAC, DATE, FPL and CASES. He was the program chair of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'18 and '19), Embedded Systems for Real-Time Multimedia (ESTIMedia '17), subcommittee chair for several editions of Design Automation and Test in Europe (DATE) conference and Brief Presentations Chair for Real-time Systems Symposium (RTSS'19) and Associate Editor for Elsevier Microprocessors and Microsystems journal for 2013-2017 and ACM Transactions on Embedded Computing Systems (TECS) special issue. He is currently an associate editor for IEEE Transactions on Circuits and Systems II, IEEE Embedded Systems Letters (ESL), IEEE Design and Test and MDPI Electronics. He was the program chair for IEEE International Conference on Field Programmable Logic and Applications 2021.

He has received Best Paper Award at DATA 2018, and best paper award nominations at DATE 2015, 2017 and 2020, FPL 2014, GLSVLSI 2014, ISVLSI 2020 and Supercomputing Conference 2015.

Introduction.- Preliminaries and Literature Reviews.- Bounding Time in Mixed-Criticality Systems.- Safety- and Task-Drop-Aware Mixed-Criticality Task Scheduling.- Learning-Based Drop-Aware Mixed-Criticality Task Scheduling.- Fault-Tolerance and Power-Aware Multi-Core Mixed-Criticality System Design.- QoS- and Power-Aware Run-Time Scheduler for Multi-Core Mixed-Criticality Systems.- Conclusion.