Number Systems for Deep Neural Network Architectures

lt;p>Ghada Alsuhli received her B.S. and M.S. degrees in electronics and communication engineering from Damascus University, Syria, in 2009 and 2015, respectively. She obtained her Ph.D. degree in electronics and communication engineering from Cairo University, Egypt, in 2019. Throughout her academic journey, she has been actively involved in research at esteemed institutions such as the National Research Center in Egypt, The American University in Cairo, Egypt, and the SOC Center at Khalifa University, UAE. Currently, Ghada holds the position of Post-Doctoral Researcher at Khalifa University, UAE, where she focuses on the design and implementation of Artificial Intelligence accelerators. Her research interests encompass a wide range of areas, including Artificial Intelligence applications in wireless communications, airborne and ground ad-hoc networks, and biomedical engineering.

Vasilis Sakellariou received his Bachelor/Master Degree in Electrical Engineering and Computer Science in University of Patras, Greece, in 2015. He is currently pursuing his PhD title in Khalifa University in Abu Dhabi. During his master he specialized in the field of microelectronics, embedded systems, integrated circuits and VLSI design, while his thesis involved designing hardware accelerators for neuromorphic computing. His current research interests are focused on designing low-power accelerators for edge-AI devices by employing non-conventional arithmetic systems, with emphasis on the Residue Numbering System, as well as emerging in-memory computing paradigms.

Hani Saleh is an associate professor of electronic engineering at Khalifa University since 2017, he joined Khalifa as assistant professor on 2012. He was a co-founder of the KSRC (Khalifa University Research Center 2012-2018) and a co-founder and a theme-lead in the System on Chip Research Center (SOCC 2019-present) where he led multiple IoT projects for the development of wearable blood glucose monitoring SOC, mobile surveillance SOC and AI Accelerators for edge devices. Hani has a total of 19 years of industrial experience in ASIC chip design, microprocessor design, DSP core design, graphics core design and embedded system design. Prior to joining Khalifa University he worked for many leading semiconductor design companies including a Senior Chip Designer (Technical Lead) at Apple incorporation, Intel (ATOM mobile microprocessor design), AMD (Bobcat mobile microprocessor design), Qualcomm (QDSP DSP core design for mobile SOC's), Synopsys (designed the I2C DW IP included in Synopys DesignWare library), Fujitsu (SPARC compatible high performance microprocessor design) and Motorola Australia. Hani received a Bachelor of Science degree in Electrical Engineering from the University of Jordan, a Master of Science degree in Electrical Engineering from the University of Texas at San Antonio, and a Ph.D. degree in Computer Engineering from the University of Texas at Austin.

Mahmoud Al-Qutayri is Professor of Electrical and Computer Engineering and the Associate Provost for Academic Operations at Khalifa University (KU), UAE. He is also affiliated with KU System-on-Chip Center, which focuses on the design of high performance and energy efficient electronic devices and systems for a wide range of applications. Prior to joining Khalifa University, he worked at De Montfort University, UK, and the University of Bath, UK. He also worked at Philips Semiconductors, Southampton, UK. Dr. Al-Qutayri has authored or coauthored numerous technical papers in peer-reviewed journals and international conferences. He has also coauthored a book entitled Digital Phase Lock Loops: Architectures and Applications and has edited a book entitled Smart Home Systems. This is in addition to a number of book chapters and patents. His current research interests include embedded systems, in-memory computing and emerging memory technologies, energy efficient IoT systems, efficient edge computing and artifi

Introduction.- Conventional number systems.- DNN architectures based on Logarithmic Number System (LNS).- DNN architectures based on Residue Number System (RNS).- DNN architectures based on Block Floating Point (BFP) number system.- DNN architectures based on Dynamic Fixed Point (DFXP) number system.- DNN architectures based on Posit number system.