Understanding Logic Locking

lt;p>Kimia Zamiri Azar is a postdoctoral research associate in the Department of Electrical and Computer Engineering at the University of Florida. She received a Ph.D. degree from the Department of Electrical and Computer Engineering at George Mason University in 2021. She also received her M.S. and B.S. from the Department of Electrical and Computer Engineering at Shahid Beheshti University, 2015, and K. N. T. University, 2013, respectively. Her research interests span hardware security and trust, supply chain security, System-on-Chips security validation and verification, and IoT security. She has multiple publications in high-prestigious journals and conferences, including IEEE Transactions on Computers, IEEE Transactions on VLSI, IACR Transactions on Cryptographic Hardware and Embedded Systems (CHES), and Design Automation Conference (DAC), with awards including nominations for Best Paper Award in IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'20 and IEEE/ACM Conference on Computer-Aided-Design (ICCAD)'21.

Hadi Mardani Kamali is a postdoctoral research associate at Florida Institute for Cybersecurity Research (FICS), the Department of Electrical and Computer Engineering at the University of Florida. He received his Ph.D. degree from the Department of Electrical and Computer Engineering at George Mason University, 2021. He received his M.S. and B.S. from the Department of Electrical and Computer Engineering at Sharif University of Technology, 2013, and K. N. T. University, 2011, respectively. His research delves into hardware security with a particular focus on exploiting IP protection techniques, design-for-trust for VLSI circuits, and CAD frameworks for security (design-for-security), in which he has numerous publications in top journals and conferences including IEEE Transactions on Computers, IEEE Transactions on VLSI, IACR Transactions on Cryptographic Hardware and Embedded Systems (CHES), and Design Automation Conference (DAC), with awards including nominations for Best Paper Award in ISVLSI'20, ICCAD'20, ICCAD'21, and IEEE CAS 2020.

Farimah Farahmandi is an assistant professor in the Department of Electrical and Computer Engineering at the University of Florida. She received her Ph.D. from the Department of Computer and Information Science and Engineering at the University of Florida, 2018. She received her B.S. and M.S. from the Department of Electrical and Computer Engineering at the University of Tehran, Iran, in 2010 and 2013, respectively. Her research interests include design automation of System-on-Chips and energy-efficient systems, formal verification, hardware security validation, and post-silicon validation and debug. Her research has resulted in two books, seven book chapters, and several publications in premier ACM/IEEE journals and conferences, including IEEE Transactions on Computers, IEEE Transactions on CAD, Design Automation Conference (DAC), and Design Automation and Test in Europe (DATE). Her research has been recognized by several awards, including IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, a nomination for the Best Paper Award in ASPDAC 2017, and DAC Richard Newton Young Student Fellowship. She has actively collaborated with various research groups (IBM, Intel, and Cisco) that have led to several joint publications. She currently serves as an Associate Editor of IET Computers & Digital Techniques. She also has served on many technical program committees as well as organizing committees of premier ACM and IEEE conferences. Her research has been sponsored by SRC, AFRL, DARPA, and Cisco. She is a member of IEEE and ACM.

Mark Tehranipoor received his Ph.D. from the University of Texas at Dallas in 2004. He is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the University of Florida. His current research projects include: hardw

Basics of VLSI Design.- Basics of VLSI Testing and Debug.- IP Protection in VLSI Design: A Historical View.- Making a Case for Logic Locking.- Fundamentals of Logic Locking.- Infrastructure around Logic Locking.- Impact of Satisfiability Solvers on Logic Locking.- Post-Satisfiability Era: Countermeasures and Threats.- Design-for-Testability and its Impact on Logic Locking.- Emergence of Cutting-edge Technologies on Logic Locking.- Logic Locking in Future IC Supply Chain Environments.- Multilayer Approach to Logic Locking.- A Step-by-Step Guide for Protecting/Locking Your IP.- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP.