Software and Compilers for Embedded Systems
Springer Berlin (Verlag)
978-3-540-20145-8 (ISBN)
Invited Talk.- The Transmeta Crusoe: VLIW Embedded in CISC.- Code Size Reduction.- Limited Address Range Architecture for Reducing Code Size in Embedded Processors.- Predicated Instructions for Code Compaction.- Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation.- Code Selection.- Code Instruction Selection Based on SSA-Graphs.- A Code Selection Method for SIMD Processors with PACK Instructions.- Reconstructing Control Flow from Predicated Assembly Code.- Loop Optimizations.- Control Flow Analysis for Recursion Removal.- An Unfolding-Based Loop Optimization Technique.- Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer.- Automatic Retargeting.- Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation.- Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models.- System Design.- A Framework for the Design and Validation of Efficient Fail-Safe Fault-Tolerant Programs.- A Case Study on a Component-Based System and Its Configuration.- Composable Code Generation for Model-Based Development.- Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor.- Register Allocation.- Retargetable Graph-Coloring Register Allocation for Irregular Architectures.- Fine-Grain Register Allocation Based on a Global Spill Costs Analysis.- Offset Assignment.- Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment.- Improving Offset Assignment through Simultaneous Variable Coalescing.- Analysis and Profiling.- Transformation of Meta-Information by Abstract Co-interpretation.- Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java.- Towards Superinstructions for Java Interpreters.- Memory and Cache Optimizations.- Partitioning for DSP Software Synthesis.- Efficient Variable Allocation to Dual Memory Banks of DSPs.- Cache Behavior Modeling of Codes with Data-Dependent Conditionals.- FICO: A Fast Instruction Cache Optimizer.
Erscheint lt. Verlag | 16.9.2003 |
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Reihe/Serie | Lecture Notes in Computer Science |
Zusatzinfo | X, 406 p. |
Verlagsort | Berlin |
Sprache | englisch |
Maße | 155 x 233 mm |
Gewicht | 585 g |
Themenwelt | Mathematik / Informatik ► Informatik ► Betriebssysteme / Server |
Mathematik / Informatik ► Informatik ► Programmiersprachen / -werkzeuge | |
Schlagworte | Architecture • code generation • code transformation • Compilation • Compiler • Compiler Optimization • Compilers • Component Systems • control flow analysis • embedded processors • Embedded Software • Embedded Systems • Extreme Programming • Hardcover, Softcover / Informatik, EDV/Programmiersprachen • HC/Informatik, EDV/Programmiersprachen • Java • Modeling • Optimization • Oval • systems configuration |
ISBN-10 | 3-540-20145-9 / 3540201459 |
ISBN-13 | 978-3-540-20145-8 / 9783540201458 |
Zustand | Neuware |
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