On-Chip Current Sensors for Reliable, Secure, and Low-Power Integrated Circuits (eBook)
XXXII, 162 Seiten
Springer International Publishing (Verlag)
978-3-030-29353-6 (ISBN)
This book provides readers with insight into an alternative approach for enhancing the reliability, security, and low power features of integrated circuit designs, related to transient faults, hardware Trojans, and power consumption. The authors explain how the addition of integrated sensors enables the detection of ionizing particles and how this information can be processed at a high layer. The discussion also includes a variety of applications, such as the detection of hardware Trojans and fault attacks, and how sensors can operate to provide different body bias levels and reduce power costs. Readers can benefit from these sensors-based approaches through designs with fast response time, non-intrusive integration on gate-level and reasonable design costs.
Rodrigo Possamai Bastos holds an engineer's degree (Electrical Engineering in 2002) and M.S. degree (Computer Science in 2006), both from Federal University of Rio Grande do Sul (UFRGS) in Porto Alegre (Brazil). He worked as a R&D engineer at DataCom Telemática in Brazil (2002 to 2004), and he completed his double Ph.D. in Nano and Microelectronics in July 2010 at UFRGS, Grenoble Institute of Technology, and TIMA Laboratory (France). From September 2010 until August 2012, he was a postdoctoral research fellow at LIRMM (France). Since September 2012, Rodrigo is an Associate Professor at Univ. Grenoble Alpes and TIMA Laboratory. In January 2018 he has obtained the French habilitation for leading research (HDR thesis).
His research interests include integrated circuit aspects related to reliability, security, and test. Rodrigo is author/co-author over 50 papers in international scientific conferences and journals, and he is a program committee member of the international IEEE conferences SBCCI, LATS, LASCAS, and ICCDCS. Rodrigo is recurrent reviewer of Elsevier Microelectronics Reliability Journal, Elsevier Microprocessors and Microsystems Journal, and IEEE Transactions on Device and Materials Reliability.
Frank Sill Torres received the Diploma and Dr.-Ing. degrees in Electrical Engineering from the University of Rostock, Germany, in 2002 and 2007, respectively. He was with the Laboratory for Optronics and Microtechnologies, Federal University of Minas Gerais (UFMG), Brazil, from 2007 to 2008, which was followed by a year in the industry. From 2010 to 2018, he was as Professor with the Department of Electronic Engineering at the UFMG where he coordinated the ASIC Reliability Group. Since 2012, he is a permanent member of the Post-graduation program in Electrical Engineering of the UFMG. In 2017, he was with the Group for Computer Architecture, Institute of Computer Science, University of Bremen, Germany. In 2018, he joined the Cyber-Physical Systems group of the German Research Center for Artificial Intelligence (DFKI) in Bremen as Senior Researcher.
His research interests include Design for Reliability, Emerging Technologies and Low-Power Integrated Circuit Design, and he is author of more than 90 publications in scientific journals, congresses and workshops. Frank Sill Torres was a member of several conference committees including ISCAS, SBCCI, LATS, MWSCAS, and the program chair of the SBCCI 2016. He is an Associate Researcher of the Brazilian National Research Council (CNPq).
Preface 5
Acknowledgments 9
Abstract 10
Contents 11
List of Abbreviations 15
List of Figures 19
List of Tables 26
About the Authors 28
1 Effects of Transient Faults in Integrated Circuits 30
1.1 Context of Transient Faults for Integrated Circuit Reliability and Security 30
1.2 Transient Faults Induced by Environmental Perturbations 32
1.3 Transient Faults Induced by Intentional Perturbations 34
1.4 Electrical-Level Effects of Transient Faults in Integrated Circuits 34
1.5 Logical-Level Effects of Transient Faults in Integrated Circuit Systems 37
1.5.1 Harmful Effects of Transient Faults on SynchronousCircuits 39
1.5.2 Harmful Effects of Transient Faults on QDI Asynchronous Circuits 39
1.5.3 Harmless Effects of Transient Faults 40
1.5.4 Failures: The Effects of Soft Errors 41
1.5.5 Harmful Effects of Long-Duration Transient Faults 42
1.5.6 Harmful Effects of Multiple Transient Faults 43
1.6 Conclusions 44
2 Effectiveness of Hardware-Level Techniques in Detecting Transient Faults 46
2.1 Techniques for Concurrent Error Detection 46
2.1.1 Spatial Redundancy 47
2.1.2 Temporal Redundancy 48
2.1.3 Transition Detector-Based Techniques 48
2.1.4 Built-In Current Sensors 49
2.2 Method for Evaluation of Concurrent Error Detection Techniques 50
2.2.1 Analysis of Injected Transient-Fault Effects 50
2.2.2 Profiles of Injected Transient Faults 51
2.2.3 Evaluation Metrics 53
2.3 Comparative Analysis of Techniques for Detection of Transient Faults 54
2.3.1 Description of Simulation Experiments 54
2.3.2 Comparative Analysis for Scenario 5 54
2.3.3 Global Comparative Analysis 54
2.4 Conclusions 56
3 Architectures of Body Built-In Current Sensors for Detection of Transient Faults 57
3.1 Fundamentals and History of Built-In Current Sensors 57
3.2 State-of-the-Art Architectures of Body Built-In Current Sensors 59
3.2.1 Single BBICS Architectures 60
3.2.2 BBICS Architectures of Neto et al. 61
3.2.3 BBICS Architectures of Zhang et al. 62
3.2.4 Modular BBICS Architectures 63
3.2.5 Dynamic BBICS Architectures of Simionovski and Wirth 66
3.2.6 Optimal Dynamic BBICS Architectures 67
3.3 Reference Sensitivity of a Flip-Flop in Detecting Transient Faults 68
3.3.1 Experiments for Analyzing the Sensitivity of a Flip-Flop in Detecting Transient Faults 69
3.3.2 Results and Analysis of the Sensitivity of a Flip-Flop in Detecting Transient Faults 70
3.4 Analysis and Comparison of Sensor Sensitivities in Detecting Transient Faults 72
3.4.1 Experiments for Sizing Sensor Architectures 72
3.4.2 Experiments for Analyzing the Sensitivities of Sensor Architectures in Detecting Transient Faults 73
3.4.3 Comparative Analysis of Sensor Sensitivities in Detecting Transient Faults 73
3.4.4 Influence of Process and Temperature Variations on the Sensor Detection Sensitivity 75
3.4.5 Influence of the Monitored Subcircuit Area on the Sensor Detection Sensitivity 76
3.5 Estimation of Sensor Area Overhead Imposed on the Monitored Subcircuit Area 77
3.6 Analysis of Sensor Sensitivity in Detecting Multiple (Simultaneous) Transient Faults 78
3.6.1 Modeling Transient Faults According to Nominal VDD of the Case-Study Subcircuit 78
3.6.2 Defining Scenarios of Multiple Transient Faults in the Case-Study Subcircuit 79
3.6.3 Finding the Critical Profiles of Transient Faults 80
3.6.4 Simulation Experiments and Results 80
Minimum Current Fall and Rise Time 80
Minimum Detectable Injected Charges 81
3.7 Conclusions 81
4 Enhancing the Design of Body Built-In Sensor Architectures 82
4.1 Concept of the Modular Body Built-In Sensor 82
4.1.1 Origination of the Approach 82
4.1.2 Basic Structure 83
4.1.3 Mode of Operation 84
4.1.4 Sizing 85
4.2 Strategies for Improving Body Built-In Sensors 86
4.2.1 Adjustable Gate Voltage on Sensing Transistor 86
4.2.2 Threshold Voltage Modification via Body-Biasing 87
4.2.3 Stack Forcing 88
4.2.4 Sizing and Voltage Levels 89
4.3 Simulation Results 90
4.3.1 Standard mBBICS 90
Simulation Environment 90
Nominal Case 91
Robustness Analysis 94
Impact of Technology Scaling 96
4.3.2 Improved mBBICS 97
Test Environment 97
Characterization 100
Robustness Analysis 102
4.3.3 Comparison to Other Works 103
4.4 Conclusions 104
5 Noise Robustness of Body Built-In Sensors 105
5.1 Motivation 105
5.2 Noise Sources 106
5.2.1 Device Noise 106
5.2.2 Switching Noise 109
5.2.3 Substrate Noise Coupling 109
5.3 Modeling 110
5.3.1 Substrate Modeling 110
5.3.2 Noise Modeling 111
5.4 Analysis Environment 112
5.4.1 Sensor Circuits 113
5.4.2 Digital Test Circuits 114
5.4.3 Influence of Simulation Time 114
5.5 Results 116
5.5.1 Exploration of Required Noise Level for SensorActivation 116
5.5.2 Distance Analysis 118
5.5.3 Noise Generation by Digital Test Circuit 119
5.5.4 Number of Monitored Transistors 122
5.5.5 Exposure Time 123
5.6 Conclusions 124
6 Body Built-In Cells for Detecting Transient Faults and Adaptively Biasing Subcircuits 125
6.1 Adaptive Body Biasing Strategy for Tuning Power and Delay of Subcircuits 125
6.1.1 FD-SOI Technology 127
6.1.2 State-of-the-Art Level Shifter (LS) Architectures 130
6.2 Architecture of Body Built-In Cells for Detecting Faults and Biasing Subcircuits 131
6.2.1 LS Structure 131
6.2.2 BBICS-Based Structure 132
6.3 Effectiveness of Body Built-In Cells in Detecting Faults and Biasing Subcircuits 133
6.3.1 Body Biasing Effectiveness 133
6.3.2 Sensitivity in Detecting Transient Faults 134
6.4 Conclusions 136
7 Automatic Integration of Body Built-In Sensors into Digital Design Flows 137
7.1 Automatic Layout Integration 137
7.1.1 Standard Cell Design 137
7.1.2 Automatic Flow for Sensor Insertion 138
7.1.3 Clustering and Head Insertion Strategies 140
Addition of Double Head Cells 140
Mixed Addition of Double and Single Head Cells 142
Addition of Tail Cells and Final Routing 142
7.1.4 Exemplary Cell Library 143
Standard Cells 144
mBBICS Cells 144
mBBICS Sensibility Estimation 146
7.1.5 Exploration 148
Environment 148
Comparison of Head Insertion Strategies 150
Impact of Benchmark Circuit 150
Maximum Load 151
Aspect Ratio 152
7.2 Light-Weight Rollback Processor Using Body Built-In Sensors 152
7.2.1 Processor Architecture 153
Basic RISC Processor 153
RISC Processor with Rollback 154
7.2.2 Results 156
7.3 Conclusions 158
8 Body Built-In Sensors for Testing Integrated Circuit Systems for Hardware Trojans 159
8.1 Testing Techniques for Detection of Hardware Trojans 159
8.2 Body Built-in Sensor-Based Testing Technique for Detection of Hardware Trojans 161
8.2.1 Injection of Current Pulses into Body Terminals of DUTT Subcircuits 162
8.2.2 Monitoring of Current Sensors Built in DUTTSubcircuits 164
8.2.3 Compilation of Signatures Collected From Subcircuit Substrate by the Sensors 165
8.2.4 Statistical Analysis for Identifying DUTT Subcircuits Infected with HT 165
8.3 Effectiveness of Body Built-in Sensors in Detecting Hardware Trojans 166
8.3.1 Description of Simulation Experiments 166
8.3.2 Target HT Implanted in DUTTs 166
8.3.3 Case-Study DUTTs and Analyses of Simulation Results 167
8.3.4 Sensor Area Overhead Imposed on the DUTT Area and Number of DUTT Samples Required for Detectinga HT 168
8.4 Conclusions 169
References 170
Index 184
| Erscheint lt. Verlag | 30.9.2019 |
|---|---|
| Zusatzinfo | XXXII, 162 p. 80 illus., 50 illus. in color. |
| Sprache | englisch |
| Themenwelt | Mathematik / Informatik ► Informatik |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | Body Built-in Sensors • Dependable embedded processors • Fault-Tolerant Systems • Radiation-Induced Transient Faults • Soft Errors |
| ISBN-10 | 3-030-29353-X / 303029353X |
| ISBN-13 | 978-3-030-29353-6 / 9783030293536 |
| Haben Sie eine Frage zum Produkt? |
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