Modeling and Application of Flexible Electronics Packaging (eBook)

Foreword 5
Preface 7
Contents 10
Abbreviations 15
1 Advanced Electronic Packaging 16
1.1 Introduction 16
1.2 Adhesively Bonded Multilayer Structure 20
1.3 Interfacial Peeling-off 21
1.3.1 Needle Ejecting for Thin Chips 21
1.3.2 Conformal Peeling for Large-Area Devices 23
1.3.3 LLO for Large-Area Flexible Electronics 24
1.4 Vacuum-Based Chip Picking-up 27
1.5 Vacuum-Based Chip Placing-on 28
1.6 Competing Fracture 31
1.6.1 Competing Fracture Behavior 31
1.6.2 Fracture Strength and Adhesive Fracture Energy 31
References 32
2 Interfacial Modeling of Flexible Multilayer Structures 43
2.1 Introduction 43
2.2 Modeling of Chip-on-Substrate Structure 43
2.2.1 Mechanical Model 43
2.2.2 Analytical Evaluation on ERR of Interfacial Peeling 45
2.2.3 Virtual Crack Closure Technique (VCCT) 47
2.2.4 Numerical Model 48
2.3 Modeling of Chip-Adhesive-Substrate Adhesively Bonded Joints 48
2.3.1 Adhesive Model on Overlapped Joints 48
2.3.2 Equilibrium Equations 50
2.3.3 Establishment of Differential Equation Set 52
2.3.4 Solutions for Internal Forces and Displacements 54
2.3.5 Relationships Among Integration Constants 58
2.3.6 Theoretical Calculation of ERR of Interfacial Peeling 60
2.4 Summary 60
References 61
3 Measurement of Fracture Strength of Ultra-thin Silicon Chip and Adhesive Fracture Energy 63
3.1 Introduction 63
3.2 Fracture Strength of Ultra-thin Silicon Chip 64
3.2.1 Experimental Procedure 64
3.2.2 Nonlinear Mechanical Characterization in Bending Test 65
3.2.3 Estimation of Fracture Strength 72
3.3 Estimation of Adhesive Fracture Energy of Adhesive Tape 76
3.3.1 Theoretical Foundation 76
3.3.2 Experimental Procedure 78
3.3.3 Estimation of Adhesive Fracture Energy 78
3.3.4 Angle Dependence of Peel Force 79
3.3.5 Rate Dependence of Adhesive Fracture Energy 81
3.4 Summary 83
References 84
4 Tension-Assisted Peeling 86
4.1 Introduction 86
4.2 Theoretical Determination of Integration Constants 86
4.2.1 Stiffened Plate Joint Under Axial Tension and Bending Moment 87
4.2.2 Single-Strap Joint Under Tension 89
4.2.3 Single-Lap Joint Under Tension 92
4.3 Modeling of Adhesively Bonded Chip Array 95
4.3.1 Mechanical Model Description 95
4.3.2 Boundary and Continuity Conditions 97
4.3.3 Solution for Internal Forces and Displacements 98
4.3.4 Determination of Integration Constants 99
4.4 Adhesive Stresses for Adhesively Bonded Joints 100
4.4.1 Analysis of Balanced Adhesively Bonded Joints 100
4.4.2 Analysis of Unbalanced Adhesively Bonded Joints 103
4.4.3 Discussion of Results 105
4.5 Peeling Behavior for Chip Array on Stretched Substrate 106
4.5.1 Adhesive Stresses 106
4.5.2 Effect of Geometric Dimensions 108
4.5.3 Effect of Material Properties 111
4.5.4 Process Optimization 113
4.6 Summary 114
References 115
5 Single-needle Peeling 117
5.1 Introduction 117
5.2 A Case for Chip-on-Substrate Structure 119
5.2.1 Effect of Crack Length 120
5.2.2 Effect of Geometric Dimensions 120
5.2.3 Effect of Elastic Mismatch 122
5.3 A Case for Chip-Adhesive-Substrate Structure 123
5.3.1 Geometric Model Description 123
5.3.2 Theoretical Calculation of ERR 127
5.3.3 Effect of Crack Length 128
5.3.4 Effect of Geometric Dimensions 129
5.3.5 Effect of Material Properties 130
5.3.6 Analysis on Tunability of Peeling Mode 131
5.4 Analysis of Fracture Mode Based on Competing Index 133
5.4.1 Typical Fracture Modes 133
5.4.2 Competing Fracture Model 135
5.4.3 Basic Fracture Parameters 136
5.4.4 Effect of Geometric Dimensions 137
5.4.5 Discussion on Results 139
5.5 Impact Effect of Needle Peeling-off Process 142
5.5.1 Failed Sample Observation 142
5.5.2 Numerical Model 142
5.5.3 Effect of Impact Speed 144
5.5.4 Effect of Substrate Penetration 146
5.6 Summary 147
References 149
6 Multi-needle Peeling 151
6.1 Introduction 151
6.2 Mechanical Model of Multi-needle Peeling-off 152
6.2.1 Model Description 152
6.2.2 Boundary and Continuity Conditions 154
6.2.3 Determination of Integration Constants 156
6.3 Competing Fracture Model of Chip-Adhesive-Substrate Structure 159
6.3.1 Modeling of Competing Fracture Behavior 159
6.4 Analysis of Bending Normal Stress and ERR of Interfacial Peeling 163
6.4.1 Analysis of Bending Normal Stress 163
6.4.2 Analysis of ERR of Interfacial Peeling 166
6.5 Effect of Chip Geometry on Competing Fracture Behavior 168
6.5.1 Effect of Chip Thickness 168
6.5.2 Effect of Chip Length 170
6.6 Experimental Validation 172
6.6.1 Experimental System 172
6.7 Summary 174
References 175
7 Conformal Peeling 177
7.1 Introduction 177
7.2 Modeling of Conformal Peeling for Multilayer Structure 178
7.3 Effect of Material Properties and Geometric Size 186
7.3.1 Effect of Young’s Modulus of Device Layer 186
7.3.2 Effect of Young’s Modulus of Adhesive Layer 188
7.3.3 Effect of Device Thickness 191
7.3.4 Effect of Substrate Thickness 193
7.3.5 Selection of Device Thickness 195
7.3.6 Selection of Substrate Thickness 197
7.4 Effects of Process Parameters 198
7.4.1 Effect of Peel Radius 198
7.4.2 Effect of Conformal Angle 198
7.4.3 Effect of Substrate Tension 199
7.5 Experimental Determination of Adhesive Fracture Energy 201
7.6 Design of Peel Blade and Its Application 206
7.6.1 Optimal Design of Peel Blade 206
7.6.2 Experimental Validation 207
7.7 Summary 210
References 211
8 Laser Lift-off 213
8.1 Introduction 213
8.2 Laser-Induced Interfacial Reaction (LIIR) 214
8.2.1 Band Gap 215
8.2.2 Laser Wavelength 216
8.2.3 Laser Fluence 216
8.2.4 Laser Irradiation Time 217
8.2.5 Laser Scanning Overlap 217
8.2.6 Physical and Chemical Properties of Material 218
8.3 Experimental Study of LLO Mechanism of Ultra-thin PI Film from Glass Carrier 218
8.3.1 Experimental Procedure 218
8.3.2 Optical Phenomena Observed After Laser Irradiation 220
8.3.3 Effects of ART and PI Film Thickness on Threshold Fluence 222
8.3.4 Typical SEM Images of PI/Glass Interface 224
8.3.5 Effects of Laser Fluence and ART on Interface Adhesion Strength 226
8.3.6 Analysis of Separation Mode 228
8.3.7 Analysis of Bubble Height 231
8.3.8 Analysis of Process Window 233
8.4 Summary 233
References 234
9 Vacuum-Based Picking-up and Placing-on 238
9.1 Introduction 238
9.2 Vacuum-Based Chip Picking-up Process 239
9.2.1 Mechanical Model 239
9.2.2 Boundary and Continuity Conditions 243
9.2.3 Determination of Integration Constants 245
9.2.4 Determination of Picking-up Criterion 246
9.2.5 Effect of Ratio of Adhesive Length to Chip Length 247
9.2.6 Effect of Ratio of VAP Below Substrate 249
9.2.7 Effect of Crack Propagation 251
9.2.8 Effects of Properties of Chip and Substrate Layers 253
9.2.9 Prediction of Chip Picking-up 256
9.2.10 Design of Chip Picking-up 257
9.3 R2R Process with Low Interfacial Residual Stress 259
9.3.1 Temperature and Force-Induced Misfits in R2R Processing 259
9.3.2 Interfacial Stress Related to Structures and Processes 262
9.3.3 Material Selection and Structural Optimization of Film-on-Substrate System 266
9.3.4 Co-optimization on Material, Structure, and Process 271
9.4 Thermal-Pressing Consolidation in Chip Placing-on Process 273
9.4.1 LWT-Based Mechanical Model 273
9.4.2 Equilibrium Equations and Solution Strategy 276
9.4.3 Boundary Conditions 279
9.4.4 Numerical Approach 279
9.4.5 Mechanism of Ultra-thin Chip Warpage 282
9.4.6 Effects of Structure Dimensions and Materials 282
9.4.7 Experimental Verification 284
9.5 Summary 287
References 288
Appendix 291