Trustworthy Hardware Design: Combinational Logic Locking Techniques

Muhammad is a PhD candidate at Tandon School of Engineering and a Global PhD Student Fellow in NYUAD. He obtained his MS in Microsystems Engineering from Masdar Institute of Science and Technology, UAE, in 2013 and BS in Elec- trical Engineering from University of Engineering and Technology (UET) Lahore, Pakistan, in 2007. He has previously served as Lecturer at COMSATS Institute of IT, Lahore. His research interests include Hardware Security and Design for Trust. Jeyavijayan Rajendran is an Assistant Professor in the Department of Elec- trical and Computer Engineering at Texas A&M University. He obtained his Ph.D. degree in the Electrical and Computer Engineering Department at New York University in August 2015. His research interests include hardware secu- rity and emerging technologies. His research has won the NSF CAREER Award in 2017, the ACM SIGDA Outstanding Ph.D. Dissertation Award in 2017, and the Alexander Hessel Award for the Best Ph.D. Dissertation in the Electrical and Computer Engineering Department at NYU in 2016. He has won three Student Paper Awards (ACM CCS 2013, IEEE DFTS 2013, and IEEE VLSI Design 2012); four ACM Student Research Competition Awards (DAC 2012, ICCAD 2013, DAC 2014, and the Grand Finals 2013); Service Recognition Award from Intel; Third place at Kaspersky American Cup, 2011; and Myron M. Rosenthal Award for Best Academic Performance in M.S. from NYU, 2011. He organizes the annual Embed- ded Security Challenge, a red-team/blue-team hardware security competition and has co-founded Hack@DAC, a student security competition co-located with DAC. He is a member of IEEE and ACM.

The Need for Logic Locking.- A Brief History of Logic Locking.- Pre-SAT Logic Locking.- The SAT Attack.- Post-SAT 1: Point function-based Logic Locking.- Approximate Attacks.- Structural Attacks.- Post-SAT 2: Insertion of SAT-unresolvable Structures.- Post-SAT 3: Stripped-Functionality Logic Locking.