ASIC/SoC Functional Design Verification (eBook)
XXXI, 328 Seiten
Springer-Verlag
978-3-319-59418-7 (ISBN)
Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium Architecture Verification team) and after a route of couple of startups, worked at Applied Micro and currently at TSMC.
He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs. At TSMC he architected and went into production with two industry standard TSMC ESL Reference Flows that take designs from ESL to RTL while preserving the verification environment for reuse from ESL to RTL.
He holds 14 U.S. Patents in the field of SoC and 3DIC design verification.
He is also the author of Second Edition of the book 'SystemVerilog Assertions and Functional Coverage - A comprehensive guide to languages, methodologies and applications'. Springer (June 2016).
Ashok earned an MSEE from University of Missouri.
In his spare time, he is an amateur photographer and likes to play drums on 70's rock music driving his neighbors up the wall J
Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium Architecture Verification team) and after a route of couple of startups, worked at Applied Micro and currently at TSMC. He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs. At TSMC he architected and went into production with two industry standard TSMC ESL Reference Flows that take designs from ESL to RTL while preserving the verification environment for reuse from ESL to RTL. He holds 14 U.S. Patents in the field of SoC and 3DIC design verification. He is also the author of Second Edition of the book “SystemVerilog Assertions and Functional Coverage – A comprehensive guide to languages, methodologies and applications”. Springer (June 2016). Ashok earned an MSEE from University of Missouri. In his spare time, he is an amateur photographer and likes to play drums on 70’s rock music driving his neighbors up the wall J
Chapter 1.Introduction.- Chapter 2.Functional Verification- Challeenges and Solution.- Chapter 3.SystemVerilog Paradigm.- Chapter 4. UVM.- Chapter 5.CRV.- Chapter 6.SVA.- Chapter 7.SFC.- Chapter 8.CDC.- Chapter 9.Low Power Verification.- Chapter 10. Static Verification.- Chapter 11.ESL.- Chapter 12. Hardware/Software Co-verification.- Chapter 13.- Analog Mixed Signals Verification.- Chapter 14.- SOC Interconnect Verification.- Chapter 15. The Complete Product Design Lifecycle.- Chapter 16. Voice Over IP.- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based.- Chapter 18. Cache Memory Subsystem Verification: ISS Based.
Erscheint lt. Verlag | 28.6.2017 |
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Zusatzinfo | XXXI, 328 p. 175 illus., 160 illus. in color. |
Verlagsort | Cham |
Sprache | englisch |
Themenwelt | Mathematik / Informatik ► Informatik |
Technik ► Elektrotechnik / Energietechnik | |
Schlagworte | Assertion Based Verifiction • Functional Hardware verification • System-on-Chip Design • System-on-Chip verification • SystemVerilog Assertions • SystemVerilog Functional Coverage |
ISBN-10 | 3-319-59418-4 / 3319594184 |
ISBN-13 | 978-3-319-59418-7 / 9783319594187 |
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